Through-silicon vias for semicondcutor substrate and method of manufacture

• US 8,487,410 B2
• Filed: 04/13/2011
• Issued: 07/16/2013
• Est. Priority Date: 04/13/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chang, Cheng-Hung, Yu, Chia-Lin, Wang, Hsiang-Yi, Wu, Tsang-Jiuh, Chiou, Wen-Chih, Liao, Ebin, Chang, Chun Hua, Huang, Li-Hsien, Kuo, Darryl
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US13/085,668
• Publication Number:
  US 20120261827A1
• Time in Patent Office: 825 Days
• Field of Search: 257/621
• US Class Current: 257/621
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 25/043 Stacked arrangements of devices
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0753 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/115 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

Claims

1. A semiconductor component comprising:

a semiconductor substrate having a top surface;

an opening having an interior surface extending from the top surface into the semiconductor substrate, wherein the opening has a top portion and a bottom portion;

a first dielectric liner disposed on the interior surface of the opening, the first dielectric liner having a thickness T₁ on the top portion and a thickness T₂ on the bottom portion, wherein R₁ is a ratio of T₁ to T₂;

a second dielectric liner disposed on the first dielectric liner, the second dielectric liner having a thickness T₃ on the top portion and a thickness T₄ on the bottom portion, wherein R₂ is a ratio of T₃ to T₄, and R₁ is greater than R₂;

a third dielectric liner disposed on the second dielectric liner, the third dielectric liner having a thickness T₅ on the top portion and a thickness T₆ on the bottom portion, wherein T₅ is greater than T₆;

a metal barrier layer disposed on the third dielectric liner; and

a conductive material disposed on the metal barrier layer and filling the opening.

2. The semiconductor component of claim 1, wherein the ratio R₁ is about 5 to about 20.

3. The semiconductor component of claim 1, wherein the ratio R₂ is about 1 to about 5.

4. The semiconductor component of claim 1, wherein a ratio R₃ of T₅ to T₆ is about 5 to about 20.

5. The semiconductor component of claim 1, wherein the first dielectric liner has a first etching rate in a HF solution, the second dielectric liner has a second etching rate in the HF solution, and the first etching rate is less than the second etching rate.

6. The semiconductor component of claim 5, wherein the third dielectric liner has a third etching rate in the HF solution, and the third etching rate is less than the second etching rate.

7. The semiconductor component of claim 1, wherein the first dielectric liner has a first compressive stress and the third dielectric liner has a second compressive stress, and at least one of the first compressive stress and the second compressive stress is within a range of 100 MPa to 400 Mpa.

8. The semiconductor component of claim 1, wherein the second dielectric liner has a tensile stress.

9. The semiconductor component of claim 8, wherein the tensile stress is within a range of 50 MPa to 300 MPa.