Package in package semiconductor device with film over wire

• US 8,487,420 B1
• Filed: 12/08/2008
• Issued: 07/16/2013
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Hwang, Chan Ha, Lee, Min Woo, Sohn, Eun Sook, Choi, Ho, Kim, Byong Jin, Yu, Ji Yeon
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US12/330,424
• Time in Patent Office: 1,681 Days
• Field of Search: 257/686, 257/777, 257/723, 257/724, 257/778, 257/787
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 2201/10378 : Interposers
• CPC Class Codes: H05K 2201/10674 : Flip chip

Abstract

In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. The semiconductor device comprises a substrate having a conductive pattern formed thereon. In each embodiment of the semiconductor device, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. In certain embodiments, a semiconductor die which is electrically connected to the conductive pattern of the substrate may be fully or partially covered with a film-over-wire. Additionally, in each embodiment of the semiconductor device, the vertically stacked electronic components thereof may be covered with a package body which also partially covers the substrate.

Claims

1. A semiconductor device, comprising:

a substrate having an electrically conductive pattern formed thereon;

a first semiconductor die disposed on the substrate and electrically connected to the conductive pattern thereof by at least one conductive wire;

a second semiconductor die disposed on the first semiconductor die and electrically connected to the conductive pattern of the substrate by at least one conductive wire;

a film-over-wire disposed on at least a portion of the second semiconductor die;

a semiconductor package positioned on the film-over-wire and electrically connected to the conductive pattern of the substrate by at least one conductive wire; and

a package body which encapsulates at least portions of the substrate, the first semiconductor die, the film over wire, the second semiconductor die and the semiconductor package, with at least one of the conductive wires being encapsulated by the package body and at least one of the conductive wires being partially encapsulated by both the film over wire and the package body.

2. The semiconductor device of claim 1 further comprising a plurality of solder balls electrically connected to the conductive pattern of the substrate.

3. The semiconductor device of claim 1 wherein the package body encapsulates a portion of the substrate, and completely encapsulates the first semiconductor die, the film over wire, the second semiconductor die and the semiconductor package.

4. The semiconductor device of claim 1 wherein the semiconductor package is positioned on and immediately adjacent to both the film-over-wire and the substrate.

5. The semiconductor device of claim 1 wherein:

the first semiconductor die defines a top surface;

the second semiconductor die defines top and side surfaces;

the film-over-wire is applied to the top surface of the first semiconductor die, and the top and side surfaces of the second semiconductor die.

6. The semiconductor device of claim 1 wherein:

the first semiconductor die defines a top surface;

the second semiconductor die defines top and side surfaces; and

the film-over-wire is applied to the top surface of the second semiconductor die.

7. The semiconductor device of claim 6 wherein the semiconductor package comprises:

an inner substrate having a conductive pattern disposed thereon, the conductive pattern of the inner substrate being electrically connected to the conductive pattern of the substrate by the at least one conductive wire;

an inner semiconductor die mounted to the inner substrate and electrically connected to the conductive pattern thereof;

an inner package body at least partially encapsulating the inner substrate and the inner semiconductor die, the inner package body defining a first surface portion which is attached and immediately adjacent to the film-over-wire and a second surface portion which is attached and immediately adjacent to the top surface of the first semiconductor die.

8. A semiconductor device, comprising:

a substrate having an electrically conductive pattern formed thereon;

a first semiconductor die electrically connected to the conductive pattern of the substrate;

a semiconductor package directly attached to the substrate by an adhesive layer and electrically connected to the conductive pattern thereof, the first semiconductor die being disposed between the substrate and a portion of the semiconductor package; and

a package body which encapsulates at least portions of the substrate, the first semiconductor die, and the semiconductor package.

9. The semiconductor device of claim 8 wherein the first semiconductor die is electrically connected to the conductive pattern of the substrate through the use of at least one conductive bump which is at least partially encapsulated by the package body, and the semiconductor package is electrically connected to the conductive pattern of the substrate through the use of at least one conductive wire which is at least partially encapsulated by the package body.

10. The semiconductor device of claim 9 wherein the semiconductor package comprises:

an inner substrate having a conductive pattern disposed thereon, the conductive pattern of the inner substrate being electrically connected to the conductive pattern of the substrate by at least one of the conductive wires;

an inner semiconductor die mounted to the inner substrate and electrically connected to the conductive pattern thereof;

an inner package body at least partially encapsulating the inner substrate and the inner semiconductor die, the inner package body defining a first surface portion which contacts the first semiconductor die, and a second surface portion which is directly attached to the substrate by the adhesive layer.

11. The semiconductor device of claim 8 wherein the first semiconductor die and the semiconductor package are each electrically connected to the conductive pattern of the substrate through the use of conductive wires which are at least partially encapsulated by the package body.

12. The semiconductor device of claim 11 wherein the semiconductor package comprises:

an inner substrate having a conductive pattern disposed thereon, the conductive pattern of the inner substrate being electrically connected to the conductive pattern of the substrate by at least one of the conductive wires;

an inner semiconductor die mounted to the inner substrate and electrically connected to the conductive pattern thereof;

an inner package body at least partially encapsulating the inner substrate and the inner semiconductor die, the inner package body defining a first surface portion having at least one through mold via disposed therein and electrically connected to the conductive pattern of the inner substrate, and a second surface portion which is directly attached to the substrate by the adhesive layer.

13. The semiconductor device of claim 12 further comprising a passive device interposed between and electrically connected to the conductive pattern of the substrate and the through mold via of the semiconductor package.

14. The semiconductor device of claim 12 further comprising a conductive bump interposed between and electrically connected to the conductive pattern of the substrate and the through mold via of the semiconductor package.

15. The semiconductor device of claim 12 wherein:

an inner substrate further comprises a third surface portion having at least one through mold via disposed therein and electrically connected to the conductive pattern of the inner substrate;

a passive device is interposed between and electrically connected to the conductive pattern of the substrate and one of the through mold via of the semiconductor package; and

a conductive bump is interposed between and electrically connected to the conductive pattern of the substrate and one of the through mold visa of the semiconductor package.

16. A semiconductor device, comprising:

a substrate having an electrically conductive pattern formed thereon;

a first semiconductor die electrically connected to the conductive pattern of the substrate through the use of conductive bumps;

a second semiconductor die disposed on the first semiconductor die and electrically connected to the conductive pattern of the substrate;

a semiconductor package stacked upon the first semiconductor die and electrically connected to the conductive pattern of the substrate, a portion of the semiconductor package being in direct contact with the second semiconductor die; and

a package body which encapsulates at least portions of the substrate, the first semiconductor die, the conductive bumps, the second semiconductor die and the semiconductor package.

17. The semiconductor device of claim 16 further comprising a spacer interposed between the semiconductor package and the first semiconductor die.

18. A semiconductor device, comprising:

a substrate having an electrically conductive pattern formed thereon;

a first semiconductor die electrically connected to the conductive pattern of the substrate through the use of conductive bumps;

a second semiconductor die directly attached to the first semiconductor die by an adhesive layer and electrically connected to the conductive pattern of the substrate;

a semiconductor package directly attached to the first semiconductor die by an adhesive layer in side-by-side relation to the second semiconductor die, and electrically connected to the conductive pattern of the substrate; and

a package body which encapsulates at least portions of the substrate, the first semiconductor die, the conductive bumps, the second semiconductor die and the semiconductor package.