Three-dimensional system-in-package architecture

• US 8,487,444 B2
• Filed: 12/04/2009
• Issued: 07/16/2013
• Est. Priority Date: 03/06/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Law, Oscar M. K., Wu, Kuo H.
• Primary Examiner(s): NGUYEN, THANH T
• Application Number:
  US12/631,346
• Publication Number:
  US 20100225002A1
• Time in Patent Office: 1,320 Days
• Field of Search: 257/774, 257/777, 257/686, 257/621
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. A semiconductor die is manufactured with both via-first TSVs as well as via-last TSVs in order to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies.

Claims

1. A semiconductor device comprising:

a first substrate of a semiconductor die;

a first plurality of dielectric layers over a first side of the first substrate;

a first via extending through the first substrate and one or more of the first plurality of dielectric layers, the first via terminating in contact with a metal line of the semiconductor die; and

a second via extending through the first substrate and two or more of the first plurality of dielectric layers, the second via extending through more of the first plurality of dielectric layers than the first via and having a first end terminating at a first side of the semiconductor die and a second end terminating at a second side of the semiconductor die.

2. The semiconductor device of claim 1, wherein the first via extends through only one of the first plurality of dielectric layers.

3. The semiconductor device of claim 1, further comprising:

an active device located on the first substrate; and

a plurality of metallization layers over the active device, wherein a first metallization layer closest to the first substrate electrically connects the first via to the active device.

4. The semiconductor device of claim 3, further comprising a conductive layer on an opposite side of the first substrate than the active device, the conductive layer in electrical contact with the first via.

5. The semiconductor device of claim 1, wherein the second via extends through each of the first plurality of dielectric layers.

6. The semiconductor device of claim 1, further comprising:

a second substrate;

a second plurality of dielectric layers;

a third via extending through the second substrate and one or more of the second plurality of dielectric layers; and

a fourth via extending through the second substrate and two or more of the second plurality of dielectric layers, the fourth via extending through more of the second plurality of dielectric layers than the third via, wherein the fourth via is electrically connected to the second via.

7. The semiconductor device of claim 6, wherein the third via is electrically connected to the first via through metallization layers located within the first plurality of dielectric layers.

8. A semiconductor device comprising:

a first semiconductor die comprising a first substrate;

a first conductive via extending through the first semiconductor die but not extending beyond the semiconductor die; and

a second conductive via extending partially through the first semiconductor die, the second conductive via extending through the first substrate and having a first end in physical contact with a conductive portion of a metallization layer of the semiconductor die, the metallization layer being electrically connected to both an active device of the first semiconductor die and a contact pad of the first semiconductor die, the contact pad being on a same side of the first semiconductor die as the active device.

9. The semiconductor device of claim 8, further comprising a plurality of dielectric layers over the first substrate, wherein the second conductive via extends through a single dielectric layer located adjacent to the first substrate.

10. The semiconductor device of claim 8, further comprising an active device on the first substrate, wherein the active device is electrically connected to the second conductive via through the metallization layer.

11. The semiconductor device of claim 10, wherein the first conductive via is surrounded by dielectric material through the semiconductor die.

12. The semiconductor device of claim 8, further comprising:

a second semiconductor die comprising a second substrate;

a third conductive via extending through the second semiconductor die, wherein the third conductive via is electrically connected to the second conductive via; and

a fourth conductive via extending less than through the second semiconductor die, the fourth conductive via extending through the second substrate.

13. The semiconductor device of claim 12, wherein the third conductive via is electrically connected to the second conductive via through metallization layers located over the substrate in the first semiconductor die.