Multi-phase clock generator

• US 8,487,682 B2
• Filed: 08/11/2011
• Issued: 07/16/2013
• Est. Priority Date: 08/11/2011
• Status: Active Grant

• Current Assignee: Hangzhou Hualan Microelectronique Co., Ltd.
• Original Assignee: Initio Corporation (Hangzhou Hualan Microelectronique Co., Ltd.)
• Inventors: Du, Zhenchang, Tang, Haiming, Wang, Wei
• Primary Examiner(s): POOS, JOHN W
• Application Number:
  US13/207,768
• Publication Number:
  US 20130038370A1
• Time in Patent Office: 705 Days
• Field of Search: 327/231, 327/238, 327/298
• US Class Current: 327/231
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 5/15093 using devices arranged in a shift register

Abstract

A clock generator includes a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal. A first phase interpolation circuit has a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch. The first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals.

Claims

1. A clock generator, comprising:

a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal and to generate a third intermediate clock phase signal in response to the clock signal and a fourth intermediate clock phase signal, the first latch including a second phase interpolation circuit having a first input coupled to a second input of the first latch and a second input coupled to a second output of the first latch; and

a first phase interpolation circuit having a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch,

wherein the first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals, and

wherein the second phase interpolation circuit is configured to output a second clock phase signal in response to receiving the third and fourth intermediate clock phase signals.

2. The clock generator of claim 1, wherein the first phase interpolation circuit includes:

a first inverter having an input coupled to the first input of the first latch and an output coupled to a first node;

a second inverter having an input coupled to the first output of the first latch and an output coupled to the first node; and

a third inverter having an input coupled to the first node and an output for outputting the first clock phase signal.

3. The clock generator of claim 1, wherein the first latch includes:

a first inverter having an input coupled to the first input of the phase interpolation circuit;

a second inverter having an input coupled to the first input of the second phase interpolation circuit;

a first transistor having a gate configured to receive the first clock signal, a drain coupled to an output of the first inverter, and a source coupled to the second input of the first phase interpolation circuit; and

a second transistor having a gate configured to receive the first clock signal, a drain coupled to an output of the second inverter, and a source coupled to the second input of the second phase interpolation circuit.

4. The clock generator of claim 1, wherein the first phase interpolation circuit includes:

a first inverter having an input coupled to the first input of the first latch and an output coupled to a first node;

a second inverter having an input coupled to the first output of the first latch and an output coupled to the first node; and

a third inverter having an input coupled to the first node and an output for outputting the first clock phase signal.

5. The clock generator of claim 4, wherein the second phase interpolation circuit includes:

a fourth inverter having an input coupled to the second input of the first latch and an output coupled to a second node;

a fifth inverter having an input coupled to the second output of the first latch and an output coupled to the first node; and

a sixth inverter having an input coupled to the second node and an output for outputting the second clock phase signal.

6. The clock generator of claim 5, further comprising a second latch having a first output coupled to the first input of the first latch and a second output coupled to the second input of the first latch.

7. The clock generator of claim 4, further comprising a second latch having a first input coupled to the first output of the first latch and a second input coupled to the second output of the first latch.

8. The clock generator of claim 4, further comprising a second latch having a first output coupled to the first input of the first latch and a second output coupled to the second input of the first latch.

9. A method, comprising:

receiving a first clock signal and a first intermediate clock phase signal at a first latch;

generating a second intermediate clock phase signal based on the first clock signal and the first intermediate clock phase signal; and

interpolating the first and second intermediate clock phase signals to provide a first clock phase signal, wherein interpolating the first and second intermediate clock phase signals includes;

combining inversions of the first and second intermediate clock phase signals to produce a combined inverted signal; and

inverting the combined inverted signal to provide the first clock phase signal.

10. The method of claim 9, further comprising:

generating a third intermediate clock phase signal in response to the first clock signal and a fourth intermediate clock phase signal; and

interpolating the third and fourth intermediate clock phase signals to provide a second clock phase signal.

11. The method of claim 10, wherein the third intermediate clock phase signal is generated at the first latch.

12. The method of claim 9, wherein the inversions of the first and second intermediate clock phase signals are combined at a node coupled to outputs of first and second inverters.

13. The method of claim 9, further comprising:

generating a third intermediate clock phase signal based on a second clock signal and the second intermediate clock phase signal; and

interpolating the second and third intermediate clock phase signals to provide a second clock phase signal.

14. A multi-phase clock generator, comprising:

a first latch configured to

output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal, and

output a third intermediate clock phase signal based on the first clock signal and a fourth intermediate clock phase signal;

a first phase interpolation circuit having a first input coupled to first input of the first latch and as second input coupled to a first output of the first latch, the first phase interpolation circuit configured to output a first clock signal based on the first and second intermediate clock phase signals; and

a second phase interpolation circuit having a first input coupled to a second input of the first latch and a second input coupled to a second output of the first latch, the second phase interpolation circuit configured to output a second clock phase signal based on the third and fourth intermediate clock phase signals.

15. The multi-phase clock generator of claim 14, wherein the first phase interpolation circuit includes:

a first inverter having an input coupled to the first input of the first latch and an output coupled to a first node;

a second inverter having an input coupled to the first output of the first latch and an output coupled to the first node; and

a third inverter having an input coupled to the first node and an output for outputting the first clock phase signal.

16. The multi-phase clock generator of claim 14, wherein the second phase interpolation circuit includes:

a first inverter having an input coupled to the second input of the first latch and an output coupled to a first node;

a second inverter having an input coupled to the second output of the first latch and an output coupled to the first node; and

a third inverter having an input coupled to the first node and an output for outputting the second clock phase signal.

17. The multi-phase clock generator of claim 14, wherein the first latch includes:

a first inverter having an input coupled to the first input of the phase interpolation circuit;

a second inverter having an input coupled to the first input of the second phase interpolation circuit;

a first transistor having a gate configured to receive the first clock signal, a drain coupled to an output of the first inverter, and a source coupled to the second input of the first phase interpolation circuit; and

a second transistor having a gate configured to receive the first clock signal, a drain coupled to an output of the second inverter, and a source coupled to the second input of the second phase interpolation circuit.

18. The multi-phase clock generator of claim 14, further comprising a second latch having a first output coupled to the first input of the first latch and a second output coupled to the second input of the first latch, the second latch configured to

output the second intermediate clock phase signal based on a second clock signal and a fifth intermediate clock phase signal, and

output the fourth intermediate clock phase signal based on the second clock signal and a sixth intermediate clock phase signal.

19. The multi-phase clock generator of claim 14, further comprising a second latch having a first input coupled to the first output of the first latch and a second input coupled to the second output of the first latch, the second latch configured to

output a fifth intermediate clock phase signal based on a second clock signal and the first intermediate clock phase signal, and

output a sixth intermediate clock phase signal based on the second clock signal and the third intermediate clock phase signal.

20. A clock generator, comprising:

a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal; and

a first phase interpolation circuit having a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch, the first phase interpolation circuit including

a first inverter having an input coupled to the first input of the first latch and an output coupled to a first node,

a second inverter having an input coupled to the first output of the first latch and an output coupled to the first node, and

a third inverter having an input coupled to the first node and an output for outputting the first clock phase signal,

wherein the first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals.

21. A method, comprising:

receiving a first clock signal and a first intermediate clock phase signal at a first latch;

generating a second intermediate clock phase signal based on the first clock signal and the first intermediate clock phase signal;

interpolating the first and second intermediate clock phase signals to provide a first clock phase signal;

generating a third intermediate clock phase signal in response to the first clock signal and a fourth intermediate clock phase signal; and

interpolating the third and fourth intermediate clock phase signals to provide a second clock phase signal.