Stacked linear power amplifier with capacitor feedback and resistor isolation
First Claim
Patent Images
1. A power amplifier circuit comprising:
- a first field effect transistor, wherein i) an RF input signal terminal is adapted to be coupled to a gate electrode of the first field effect transistor and ii) a first DC control voltage input is adapted to be coupled to the gate electrode of the first field effect transistor;
one or more additional serially connected field effect transistors serially connected among themselves and to the first field effect transistor, each having a source terminal connected to a drain terminal of a preceding field effect transistor, wherein one or more additional DC control voltage inputs are each coupled to respective gate electrodes of the one or more additional field effect transistors, an output of the power amplifier circuit being taken on a drain electrode of the last one of the one or more additional field effect transistors; and
one or more capacitors, each coupled to a respective one of the one or more additional field effect transistors,wherein the first DC control voltage input, the one or more additional DC control voltage inputs and the one or more capacitors are selected to minimize generation of non-linearities of each field effect transistor of the power amplifier circuit and/or to maximize, through phase alignment, cancellation of distortions between the field effect transistors of the power amplifier circuit whereby, upon minimization of non-linearities and/or maximization of cancellation of distortions, at least two of the first field effect transistor and the one or more additional field effect transistors are biased with different drain-source voltages Vds, different gate-source voltages Vgs and/or different drain currents Id.
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Abstract
A power amplifier with stacked, serially connected, field effect transistors is described. DC control voltage inputs are fed to the gates of each transistor. Capacitors are coupled to the transistors. The inputs and the capacitors are controlled to minimize generation of non-linearities of each field effect transistor and/or to maximize cancellation of distortions between the field effect transistors of the power amplifier in order to improve linearity of the power amplifier output.
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Citations
20 Claims
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1. A power amplifier circuit comprising:
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a first field effect transistor, wherein i) an RF input signal terminal is adapted to be coupled to a gate electrode of the first field effect transistor and ii) a first DC control voltage input is adapted to be coupled to the gate electrode of the first field effect transistor; one or more additional serially connected field effect transistors serially connected among themselves and to the first field effect transistor, each having a source terminal connected to a drain terminal of a preceding field effect transistor, wherein one or more additional DC control voltage inputs are each coupled to respective gate electrodes of the one or more additional field effect transistors, an output of the power amplifier circuit being taken on a drain electrode of the last one of the one or more additional field effect transistors; and one or more capacitors, each coupled to a respective one of the one or more additional field effect transistors, wherein the first DC control voltage input, the one or more additional DC control voltage inputs and the one or more capacitors are selected to minimize generation of non-linearities of each field effect transistor of the power amplifier circuit and/or to maximize, through phase alignment, cancellation of distortions between the field effect transistors of the power amplifier circuit whereby, upon minimization of non-linearities and/or maximization of cancellation of distortions, at least two of the first field effect transistor and the one or more additional field effect transistors are biased with different drain-source voltages Vds, different gate-source voltages Vgs and/or different drain currents Id. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A power amplifier comprising a plurality of amplifying components connected in parallel, each amplifying component comprising:
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a) a first field effect transistor wherein a first DC control voltage input is adapted to be coupled to a gate terminal of the first field effect transistor; b) one or more additional serially connected field effect transistors serially connected among themselves and to the first field effect transistor, each having a source terminal connected to a drain terminal of a preceding field effect transistor, wherein one or more additional DC control voltage inputs are each coupled to respective gate terminals of the one or more additional field effect transistors; and c) one or more capacitors, each coupled to a respective one of the one or more additional field effect transistor, wherein i) an RF input signal terminal is adapted to be coupled to the gate terminal of the first field effect transistor of each amplifying component, thus providing the power amplifier with the same input to each amplifying component; ii) an output of the power amplifier is taken on the drain terminal of the last one of the one or more additional field effect transistors of each amplifying component, thus providing the power amplifier with the same output from each amplifying component; and iii) the first DC control voltage input, the one or more additional DC control voltage inputs and the one or more capacitors of at least one amplifying component are selected to minimize generation of non-linearities of each field effect transistor of the power amplifier circuit and/or to maximize, through phase alignment, cancellation of distortions between the field effect transistors of the power amplifier whereby, upon minimization of non-linearities and/or maximization of cancellation of distortions, at least two of the first field effect transistor and the one or more additional field effect transistors of the at least one amplifying component are biased with different drain-source voltages Vds, gate-source voltages Vgs and/or drain currents Id. - View Dependent Claims (13, 14, 15, 16)
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17. A method for controlling DC voltage inputs and capacitance values of a power amplifier, comprising:
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providing a first field effect transistor, wherein i) an RF input signal terminal is adapted to be coupled to a gate electrode of the first field effect transistor and ii) a first DC control voltage input is adapted to be coupled to the gate electrode of the first field effect transistor; providing one or more additional serially connected field effect transistors serially connected among themselves and to the first field effect transistor, each having a source terminal connected to a drain terminal of a preceding field effect transistor, wherein one or more additional DC control voltage inputs are each coupled to respective gate electrodes of the one or more additional field effect transistors, an output of the power amplifier circuit being taken on a drain electrode of the last one of the one or more additional field effect transistors; providing one or more capacitors, each coupled to a respective one of the one or more additional field effect transistor; and controlling the first DC control voltage input, the one or more additional DC control voltage inputs and the one or more capacitors to minimize generation of non-linearities of each field effect transistor of the power amplifier circuit and/or to maximize, through phase alignment, cancellation of distortions between the field effect transistors of the power amplifier circuit whereby, upon minimization of non-linearities and/or maximization of cancellation of distortions, at least two of the first field effect transistor and the one or more additional field effect transistors are biased with different drain-source voltages Vds, different gate-source voltages Vgs and/or different drain currents Id. - View Dependent Claims (18)
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19. A method for controlling DC voltage inputs and capacitance values of a power amplifier, comprising:
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a) providing a first field effect transistor, wherein a first DC control voltage input is adapted to be coupled to a gate terminal of the first field effect transistor; b) providing one or more additional serially connected field effect transistors serially connected among themselves and to the first field effect transistor, each having a source terminal connected to a drain terminal of a preceding field effect transistor, wherein one or more additional DC control voltage inputs are each coupled to respective gate terminals of the one or more additional field effect transistors; and c) providing one or more capacitors, each coupled to a respective one of the one or more additional field effect transistor, wherein; i) an RF input signal terminal is adapted to be coupled to the gate terminal of the first field effect transistor of each amplifying component, thus providing the power amplifier with the same input to each amplifying component; and ii) an output of the power amplifier is taken on the drain terminal of the last one of the one or more additional field effect transistors of each amplifying component, thus providing the power amplifier with the same output from each amplifying component, the method further comprising d) controlling the first DC control voltage input, the one or more additional DC control voltage inputs and the one or more capacitors of at least one amplifying component to minimize generation of non-linearities of each field effect transistor of the power amplifier circuit and/or to maximize, through phase alignment, cancellation of distortions between the field effect transistors of the power amplifier whereby, upon minimization of non-linearities and/or maximization of cancellation of distortions, at least two of the first field effect transistor and the one or more additional field effect transistors of the at least one amplifying component are biased with different drain-source voltages Vds, different gate-source voltages Vgs and/or different drain currents Id. - View Dependent Claims (20)
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Specification