Chemical detection circuit including a serializer circuit

• US 8,487,790 B2
• Filed: 06/30/2011
• Issued: 07/16/2013
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Fife, Keith, Yang, Jungwook
• Primary Examiner(s): Mai, Lam T
• Application Number:
  US13/174,562
• Publication Number:
  US 20120001779A1
• Time in Patent Office: 747 Days
• Field of Search: 436/149, 436/150, 436/151, 436/164, 436/167, 436/181, 356/301, 356/342, 250/208.1, 327/536, 435/286.1, 435/287.2, 257/253, 257/252, 257/E29.3, 257/E33.012, 257/E27.06, 204/406, 422/82.01, 324/71.5
• US Class Current: 341/101
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: G01N 27/4143 Air gap between gate and channel, i.e. suspended gate [SG] FETs work function measurement per se G01N27/002
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G01N 33/00 Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
• CPC Class Codes: G01R 29/26 Measuring noise figure; Measuring signal-to-noise ratio
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: Y10T 436/25875 Gaseous sample or with change of physical state

Abstract

The described embodiments may provide a chemical detection circuit. The chemical detection circuit may comprise a pixel array, a pair of analog-to-digital converter (ADC) circuit blocks, a pair of input/output (I/O) circuit blocks coupled to the pair of ADC circuit blocks respectively, and a plurality of serial link terminals coupled to the pair of IO circuit blocks. The pixel array may comprise a plurality of chemically-sensitive pixels formed in columns and rows. Each chemically-sensitive pixel may comprise: a chemically-sensitive transistor, and a row selection device.

Claims

1. A chemical detection circuit, comprising:

a pixel array comprising a plurality of chemically-sensitive pixels formed in columns and rows, each chemically-sensitive pixel comprising;

a chemically-sensitive transistor; and

a row selection device;

a pair of analog-to-digital converter (ADC) circuit blocks coupled to the pixel array;

a pair of input/output (I/O) circuit blocks coupled to the pair of ADC circuit blocks respectively; and

a plurality of serial link terminals coupled to the pair of I/O circuit blocks.

2. The chemical detection circuit of claim 1, wherein each one of the I/O circuit blocks includes a plurality of latches and a plurality of serializers.

3. The chemical detection circuit of claim 2, wherein each serializer is coupled between a latch and a respective one of the serial link terminals.

4. The chemical detection circuit of claim 3, wherein each one of the serial link terminals contains a driver coupled to two pins.

5. The chemical detection circuit of claim 4, wherein the driver is configured to work in one of two modes:

driving the two pins with a differential data pair; and

driving the two pins with two data bits in parallel.

6. The chemical detection circuit of claim 2, wherein each serializer includes a multiplexer to select one of two inputs:

built-in self test data and data generated by the chemically-sensitive pixel.

7. The chemical detection circuit of claim 1, wherein each of the serial link terminals transmits data bits by a differential signaling scheme through a transmission line.

8. The chemical detection circuit of claim 7, wherein the differential signaling is one of low-voltage differential signaling and current mode logic.

9. The chemical detection circuit of claim 1, wherein the pair of ADC circuit blocks include a respective ADC for each column of chemically-sensitive pixels.

10. The chemical detection circuit of claim 1, wherein the I/O circuit blocks contain memory to pipeline the data transfer from the pair of ADC circuit blocks to the IO circuit blocks such that a new analog-to-digital conversion process can begin while the previous data is read from the memory buffer.

11. The chemical detection circuit of claim 1, wherein the pair of ADC circuit blocks include respective ADCs shared between multiple columns of chemically-sensitive pixels.

12. The chemical detection circuit of claim 1, wherein the I/O circuit blocks contain programmable configuration registers for changing a physical driver protocol depending on the interface requirements.

13. A method to read out data from a chemical detection device, comprising:

reading data from a plurality of columns of chemically-sensitive pixels on the chemical detection device in parallel, wherein each chemically-sensitive pixel comprises;

a chemically-sensitive transistor; and

a row selection device;

digitizing data read from the plurality of columns of chemically-sensitive pixels in parallel;

serializing the digitized data in parallel for each column of chemically-sensitive pixels respectively; and

transmitting the buffered digitized data on a plurality of serial links in parallel.

14. The method of claim 13, wherein the transmitting the buffered digitized data is carried out using lowvoltage differential signaling (LVDS) or current mode logic (CML) via an impedance controlled transmission line.

15. The method of claim 13, wherein the transmitting the buffered digitized data is carried out using lowspeed full rail-to-rail signaling for convenience in testing devices where a high speed transmission line cannot be implemented.

16. The method of claim 13, further comprising:

pipelining data transfer from ADC circuit blocks to IO circuit blocks such that a new analog-to-digital conversion process can begin while the buffered digitized data is read from a memory buffer.

17. The method of claim 13, wherein the transmitting the buffered digitized data is carried out using lowspeed full rail-to-rail signaling for convenience in testing devices where a high speed transmission line cannot be implemented.