5T high density nvDRAM cell

• US 8,488,379 B2
• Filed: 10/11/2011
• Issued: 07/16/2013
• Est. Priority Date: 12/31/2007
• Status: Expired due to Fees

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Scade, Andreas, Guenther, Stefan
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/270,995
• Publication Number:
  US 20120113718A1
• Time in Patent Office: 644 Days
• Field of Search: None
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor

Abstract

A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.

Claims

1. A memory circuit, comprising:

a non-volatile bit storage region (“

nv region”

) configured to store a non-volatile bit value;

a volatile bit storage region (“

v region”

) configured to store at least part of a volatile bit value;

a control circuit to control voltage levels applied to the nv region and the v region during memory operations;

an isolation circuit configured to selectively create or remove electrical isolation between the v region and the nv region when operated by the control circuit;

the control circuit configured to perform a STORE memory operation by;

operating the isolation region to remove electrical isolation between the nv region and the v region;

setting the non-volatile bit value to the volatile bit value; and

after the non-volatile bit value is stored, refreshing the volatile bit value to the value it had before the non-volatile bit value was set.

2. The memory circuit of claim 1, further comprising:

the control circuit configured to apply voltages of greater magnitude than logical one to a charge storage element of the nv region during the STORE.

3. The memory circuit of claim 1, further comprising:

the control circuit configured to preserve the value of the volatile bit on a bit line; and

the control circuit configured to set the volatile bit value from the bit line to the v region after the non-volatile bit value is stored.

4. The memory circuit of claim 3, further comprising:

the control circuit configured to remove isolation between the nv region and the v region until the volatile bit value in the v region is set from the bit line.

5. The memory circuit of claim 1, further comprising:

the volatile bit value stored by one or more transistors that also store the non-volatile bit value.

6. The memory circuit of claim 5, further comprising:

the nv region comprising a single SONOS transistor that stores the non-volatile bit value and a portion of the volatile bit value.

7. The memory circuit of claim 1, further comprising:

the volatile bit value stored only by circuit elements that do not also store the non-volatile bit value.

8. The memory circuit of claim 1, further comprising:

the nv region consisting of a single SONOS transistor.

9. The memory circuit of claim 7, further comprising:

the v region comprising a single transistor.

10. The memory circuit of claim 1, further comprising:

the volatile bit value stored exclusively by one or more elements of the v region and the isolation region.

11. The memory circuit of claim 1, further comprising:

the nv region, isolation region, and v region together formed by five transistors configured to switch in series between a current supply terminal and a bit line.

12. The memory circuit of claim 1, further comprising:

the v region comprising a capacitor configured in series between transistors of the isolation region.

13. The memory circuit of claim 1, further comprising:

the v region and isolation region together consisting of three transistors in series.

14. A memory circuit, comprising:

a first region providing storage of a value of a nonvolatile bit;

a second region providing storage of at least part of a value of a volatile bit;

an isolation region configured to be operated to electrically isolate the first region from the second region;

a current source;

a control circuit configured to apply voltages to operate the first region, the second region, the isolation region, and the current source to perform a RECALL memory operation, by;

removing electrical isolation between the first region and the second region;

driving current from the current source through the first region and through the second region to a bit line when the value of the nonvolatile bit is a first value;

preventing current from flowing through the first region and through the second region to a bit line when the value of the nonvolatile bit is a second value;

setting the volatile bit value to a bit value on the bit line; and

restoring electrical isolation between the first region and the second region.

15. The memory circuit of claim 14, further comprising:

sensing the bit value on the bit line as a current flow from the first region to the bit line.

16. The memory circuit of claim 14, further comprising:

the first value is a logical one, and the second value is a logical zero.

17. The memory circuit of claim 14, further comprising:

the second region and isolation region together consisting of three transistors in series.

18. The memory circuit of claim 14, further comprising:

the value of the volatile bit stored by one or more transistors that also store the value of the non-volatile bit.

19. The memory circuit of claim 14, further comprising:

the first region consisting of a single SONOS transistor.

20. The memory circuit of claim 14, further comprising:

the value of the volatile bit stored by one or more transistors of the second region and the isolation region.