Non-volatile memory device having vertical structure and method of operating the same

• US 8,488,381 B2
• Filed: 08/20/2010
• Issued: 07/16/2013
• Est. Priority Date: 02/02/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Doogon, Shim, Sunil, Kim, Hansoo, Cho, Wonseok, Jang, Jaehoon, Jeong, Jaehun
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US12/860,049
• Publication Number:
  US 20100315875A1
• Time in Patent Office: 1,061 Days
• Field of Search: 365/185.11, 365/185.17, 365/185.18, 365/185.28
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.

Claims

1. A non-volatile memory device comprising:

a memory cell array; and

a peripheral circuit configured to access the memory cell array,

wherein the memory cell array includes;

a substrate;

a plurality of memory cell groups arranged in rows and columns on the substrate, each memory cell group including a plurality of memory cells stacked in series;

a plurality of first select transistor groups coupled between the substrate and the plurality of memory cell groups respectively; and

a plurality of second select transistor groups respectively coupled between the plurality of memory cell groups and a plurality of bit lines,

wherein the plurality of memory cell groups, the plurality of first select transistor groups, and the plurality of second select transistor groups form a plurality of memory cell strings extending from the substrate, each memory cell string comprising a first select transistor group coupled between a first end of a memory cell group and the substrate and a second select transistor group coupled between a second end of the memory cell group and a bit line,

wherein the peripheral circuit is configured to independently drive second select transistors of a second select transistor group corresponding to an unselected memory cell group of the plurality of memory cell groups during a program operation, and

wherein a second select transistor group of a selected memory cell group is configured to receive a turn-on voltage during the program operation.

2. The non-volatile memory device of claim 1, wherein the peripheral circuit is further configured to drive the second select transistors of the second select transistor group with different voltages during a program operation.

3. The non-volatile memory device of claim 1, wherein a specific second select transistor of the second select transistor group is driven with a first voltage, and another second select transistor of the second select transistor group provided between the specific second select transistor and the unselected memory cell group is driven with a second voltage higher than the first voltage during a program operation.

4. The non-volatile memory device of claim 3, wherein the first voltage has a level higher than a ground voltage.

5. The non-volatile memory device of claim 3, wherein the second voltage has a level to turn on the another second select transistor.

6. The non-volatile memory device of claim 3, wherein the second voltage has a level to turn off the another second select transistor.

7. The non-volatile memory device of claim 1, wherein second select transistors of each second select transistor group are connected to the peripheral circuit through different metal layers respectively.

8. The non-volatile memory device of claim 1, wherein first select transistors of each first select transistor group are driven commonly.

9. The non-volatile memory device of claim 1, wherein first select transistors of each first select transistor group are connected commonly on a metal layer.

10. The non-volatile memory device of claim 1, wherein memory cells having identical sequence from the substrate are driven commonly.

11. The non-volatile device of claim 1, wherein memory cells having identical sequence from the substrate are connected commonly on a metal layer.

12. A memory system comprising:

a non-volatile memory device; and

a controller configured to control the non-volatile memory device,

wherein the non-volatile memory device includes a memory cell array and a peripheral circuit configured to access the memory cell array,

wherein the memory cell array includes a plurality of memory cell strings having 3 dimensional structure, each memory cell string including at least two first select transistors coupled between a substrate and a first end of a serially connected memory cell group and at least two second select transistors coupled between a bit line and a second end of the memory cell group,

wherein the peripheral circuit is configured to drive the at least two second select transistors of an unselected memory cell string of the plurality of memory cell strings with different voltages during a program operation, and

wherein at least two second select transistors of a selected memory cell string is configured to receive a turn-on voltage during the program operation.

13. The memory system of claim 12, wherein a specific second select transistor of the at least two second select transistors of the unselected memory cell string is driven with a first voltage, and another second select transistor of the at least two second select transistors of the unselected memory cell string provided between the specific second select transistor and memory cells is driven with a second voltage having a level higher than the first voltage during a program operation.

14. The memory system of claim 12, wherein the non-volatile memory device and the controller forms a solid state drive SSD.