Scalable packet-switch

• US 8,488,489 B2
• Filed: 06/16/2009
• Issued: 07/16/2013
• Est. Priority Date: 06/16/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Manzella, Joseph A.
• Primary Examiner(s): Shah, Chirag
• Assistant Examiner(s): MITCHELL, DANIEL D
• Application Number:
  US12/485,164
• Publication Number:
  US 20100316062A1
• Time in Patent Office: 1,491 Days
• Field of Search: None
• US Class Current: 370/254
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches

Abstract

A scalable packet switch possessing a multiport memory, a multiport memory manager, two or more input/output (I/O) ports, and two or more switch engines. Each switch engine is associated with one or more I/O ports, and is adapted to receive inbound packets and transmit outbound packets via the associated I/O ports. Inbound packets are stored in a shared packet buffer. Each switch engine is further adapted to (i) determine (i.e., bridge) the outbound I/O port(s) for received inbound packets by consulting a shared bridging table and (ii) schedule outbound packets for transmission, independently and in parallel with other switch engines. The shared packet buffer and shared bridging table are stored in the multiport memory and shared by all switch engines. The multiport memory manager allocates/de-allocates memory blocks within the multiport memory.

Claims

1. A packet switch comprising:

two or more switch engines;

two or more sets of one or more input/output (I/O) ports, each set of I/O ports connected to and associated with a corresponding switch engine;

one or more shared memory devices connected to the two or more switch engines and configured to store;

egress task data for two or more sets of one or more egress task queues, each set of egress task queues associated with a corresponding switch engine; and

packet data for packets received at the I/O ports and processed by the switch engines, wherein;

the two or more switch engines are configured to process packets in parallel;

each switch engine performs (i) bridging of received packets using bridging logic local to the switch engine and (ii) scheduling of received packets for transmission using scheduling logic local to the switch engine;

the one or more shared memory devices are configured to store a shared bridging table accessed by each switch engine to perform the bridging; and

each switch engine is further configured to perform access-control-list (ACL) filtering comprising consulting an ACL table and rendering a decision whether to mirror a received packet.

2. The packet switch of claim 1, wherein the processing of packets by each switch engine is independent of the processing of packets by each other switch engine.

3. The packet switch of claim 1, wherein the one or more shared memory devices are a single multiport memory device.

4. The packet switch of claim 1, wherein the packet data for each of the received packets is stored in a shared packet buffer in the one or more shared memory devices.

5. The packet switch of claim 1, further comprising a memory manager connected to control writing data to and reading data from the one or more shared memory devices.

6. The packet switch of claim 1, wherein each switch engine performs bridging using a bridging table local to the switch engine.

7. The packet switch of claim 1, wherein each switch engine further performs background aging of records in a bridging table.

8. The packet switch of claim 1, Wherein each switch engine performs the ACL filtering of received packets using ACL logic local to the switch engine.

9. The packet switch of claim 8, wherein the one or more shared memory devices store a shared ACL table accessed by each switch engine to perform the ACL filtering.

10. The packet switch of claim 8, wherein each switch engine performs the ACL filtering using an ACL table local to the switch engine.

11. The packet switch of claim 1, wherein the two or more switches communicate with each other via an engine communication ring.

12. The packet switch of claim 1, wherein:

a first switch engine is configured to receive a received packet from one of its I/O ports and process the received packet for storage in the one or more shared memory devices; and

a second switch engine, different from the first switch engine, is configured to retrieve the received packet from the one or more shared memory devices and transmit the received packet via one of its I/O ports.

13. The packet switch of claim 1, wherein:

the processing of packets by each switch engine is independent of the processing of packets by each other switch engine;

the one or more shared memory devices are a single multiport memory device;

the packet data for the received packets is stored in a shared packet buffer in the multiport memory device;

the packet switch further comprises a memory manager connected to control writing data to and reading data from the multiport memory device;

each switch engine further performs the ACL filtering of received packets using ACL logic local to the switch engine;

the multiport memory device stores a shared ACL table accessed by each switch engine to perform the ACL filtering;

the two or more switches communicate with each other via an engine communication ring;

a first switch engine is configured to receive a received packet from one of its I/O ports and process the received packet for storage in the multiport memory device; and

a second switch engine, different from the first switch engine, is configured to retrieve the received packet from the multiport memory device and transmit the received packet via one of its I/O ports.

14. The packet switch of claim 1, wherein each switch engine is configured to perform background aging of only a subset of the records in the shared bridging table.

15. A communications system having a plurality of interconnected packet switches, at least one packet switch comprising:

two or more switch engines;

two or more sets of one or more input/output (I/O) ports, each set of I/O ports connected to and associated with a corresponding switch engine;

one or more shared memory devices connected to the two or more switch engines and configured to store;

egress task data for two or more sets of one or more egress task queues, each set of egress task queues associated with a corresponding switch engine; and

packet data for packets received at the I/O ports and processed by the switch engines, wherein;

the two or more switch engines are configured to process packets in parallel;

each switch engine performs (i) bridging of received packets using bridging logic local to the switch engine and (ii) scheduling of received packets for transmission using scheduling logic local to the switch engine;

the one or more shared memory devices are configured to store a shared bridging table accessed by each switch engine to perform the bridging; and

each switch engine is further configured to perform access-control-list (ACL) filtering comprising consulting an ACL table and rendering a decision whether to mirror a received packet.

16. The communication system of claim 15, wherein:

the processing of packets by each switch engine is independent of the processing of packets by each other switch engine;

the one or more shared memory devices are a single multiport memory device;

the packet data for the received packets is stored in a shared packet buffer in the multiport memory device;

the packet switch further comprises a memory manager connected to control writing data to and reading data from the multiport memory device;

each switch engine further performs the ACL filtering of received packets using ACL logic local to the switch engine;

the multiport memory device stores a shared ACL table accessed by each switch engine to perform the ACL filtering;

the two or more switches communicate with each other via an engine communication ring;

a first switch engine is configured to receive a received packet from one of its I/O ports and process the received packet for storage in the multiport memory device; and

a second switch engine, different from the first switch engine, is configured to retrieve the received packet from the multiport memory device and transmit the received packet via one of its I/O ports.