Disabling outbound drivers for a last memory buffer on a memory channel

• US 8,489,944 B2
• Filed: 12/03/2012
• Issued: 07/16/2013
• Est. Priority Date: 06/05/2003
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Morrow, Warren, Vogt, Pete, Brzezinski, Dennis W.
• Primary Examiner(s): TRIMMINGS, JOHN P
• Application Number:
  US13/692,355
• Publication Number:
  US 20130097371A1
• Time in Patent Office: 225 Days
• Field of Search: None
• US Class Current: 714/718
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4256 using a clocked protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Claims

1. An integrated circuit to provide a memory buffer to isolate one or more dynamic random access memory devices (DRAM devices) from a point-to-point channel, the integrated circuit comprising:

an inbound redrive circuit to receive and redrive signals on an inbound path of the point-to-point channel, the inbound redrive circuit including, at least in part, two or more bit-lanes for the inbound path of the point-to-point channel;

an outbound redrive circuit to receive and redrive signals on an outbound path of the point-to-point channel, the outbound redrive circuit including, at least in part, two or more bit-lanes for the outbound path of the point-to-point channel;

logic coupled with the outbound path of the point-to-point channel, the logic to calibrate a newly appended memory agent responsive, at least in part, to receiving a command; and

a double data rate (DDR) memory interface to couple the memory buffer with the one or more DRAM devices, the memory interface to receive data from the outbound redrive circuit and to send data to the inbound redrive circuit.

2. The integrated circuit of claim 1, wherein the logic to calibrate the newly appended memory agent responsive, at least in part, to the command from the host includes logic to implement, at least in part, a fast reset operation.

3. The integrated circuit of claim 1, wherein the newly appended memory agent is a newly appended memory module.

4. The integrated circuit of claim 1, wherein the newly appended memory agent is a newly appended memory buffer.

5. The integrated circuit of claim 1, wherein at least one DRAM device is a DDR2 DRAM device.

6. The integrated circuit of claim 1, wherein the memory buffer is coupled to the point-to-point channel.

7. The integrated circuit of claim 1, wherein a host is coupled to the point-to-point channel.

8. The integrated circuit of claim 1, wherein the logic coupled with the point-to-point channel, the logic to calibrate a newly appended memory agent responsive, at least in part, to a command from a host comprises logic coupled to the outbound path of the point-to-point channel.

9. The integrated circuit of claim 1, wherein the logic to calibrate the newly appended memory agent comprises logic to calibrate the impendence of an input/output circuit.

10. The integrated circuit of claim 1, wherein the logic to calibrate the newly appended memory agent comprises logic to calibrate a current source.

11. A system comprising:

a host; and

an integrated circuit coupled with the host, the integrated circuit to provide a memory buffer to isolate one or more dynamic random access memory devices (DRAM devices) from a point-to-point channel, the integrated circuit including,

an inbound redrive circuit to receive and redrive signals on an inbound path of the point-to-point channel, the inbound redrive circuit including, at least in part, two or more bit-lanes for the inbound path of the point-to-point channel,

an outbound redrive circuit to receive and redrive signals on an outbound path of the point-to-point channel, the outbound redrive circuit including, at least in part, two or more bit-lanes for the outbound path of the point-to-point channel,

logic coupled with the outbound path of the point-to-point channel, the logic to calibrate a newly appended memory agent responsive, at least in part, to a command from the host, and

a double data rate (DDR) memory interface to couple the memory buffer with the one or more DRAM devices, the memory interface to receive data from the outbound redrive circuit and to send data to the inbound redrive circuit.

12. The system of claim 11, wherein the host is a processor.

13. The system of claim 12, wherein the host initiates a fast reset operation after the logic calibrates the newly appended memory agent.

14. The system of claim 11, wherein the newly appended memory agent is a newly appended memory module.

15. The system of claim 11, wherein the newly appended memory agent is a newly appended memory buffer.