Solid-state mass storage device and method for failure anticipation

• US 8,489,966 B2
• Filed: 01/07/2011
• Issued: 07/16/2013
• Est. Priority Date: 01/08/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: OCZ Technology Group, Inc. (Toshiba Corporation)
• Inventors: Schuette, Franz Michael, Filor, Lutz
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US12/986,564
• Publication Number:
  US 20110173484A1
• Time in Patent Office: 921 Days
• Field of Search: 714/774
• US Class Current: 714/773
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A solid-state mass storage device and method of operating the storage device to anticipate the failure of at least one memory device thereof before a write endurance limitation is reached. The method includes assigning at least a first memory block of the memory device as a wear indicator that is excluded from use as data storage, using pages of at least a set of memory blocks of the memory device for data storage, writing data to and erasing data from each memory block of the set in program/erase (P/E) cycles, performing wear leveling on the set of memory blocks, subjecting the wear indicator to more P/E cycles than the set of memory blocks, performing integrity checks of the wear indicator and monitoring its bit error rate, and taking corrective action if the bit error rate increases.

Claims

1. A method for predicting failure of a solid-state mass storage device having a controller and at least one nonvolatile memory device comprising pages that are organized into memory blocks, the method comprising:

assigning at least a first of the memory blocks as wear indicator means and excluding the wear indicator means from use as data storage for the nonvolatile memory device;

using at least a set of the memory blocks of the nonvolatile memory device for data storage whereby data are written to and erased from each memory block of the set of memory blocks in program/erase (P/E) cycles;

collecting information regarding the number of P/E cycles encountered by the memory blocks of the set of memory blocks and accessing the information to perform wear leveling on the set of memory blocks;

subjecting the wear indicator means to P/E cycles so that the wear indicator means is subjected to a number of P/E cycles that is greater than the number of P/E cycles encountered by the memory blocks of the set of memory blocks;

performing integrity checks of the wear indicator means and monitoring a bit error rate thereof; and

taking corrective action if the bit error rate of the wear indicator means increases.

2. The method of claim 1, wherein the wear indicator means comprises a plurality but not all of the pages of at least some of the memory blocks of the nonvolatile memory device.

3. The method of claim 1, wherein the wear indicator means comprises all of the pages of at least the first memory block of the nonvolatile memory device.

4. The method of claim 1, wherein the wear indicator means comprises all of the pages of only the first memory block of the nonvolatile memory device.

5. The method of claim 1, wherein the P/E cycles to which the wear indicator means are subjected preferentially write 0 bit values to the wear indicator means.

6. The method of claim 1, wherein the P/E cycles to which the wear indicator means are subjected preferentially write 0 bit values to a first set of the wear indicator means, preferentially write 1 bit values to a second set of the wear indicator means, and write a mix of 0 bit and 1 bit values to a third set of the wear-indicator means.

7. The method of claim 1, wherein the number of P/E cycles to which the wear indicator means is subjected is greater than the number of P/E cycles encountered by the memory blocks of the set of memory blocks by a non-zero offset value.

8. The method of claim 7, wherein the non-zero offset value is relative to an average of the number of P/E cycles encountered by the memory blocks of the set of memory blocks.

9. The method of claim 1, wherein the subjecting step comprises subjecting the wear indicator means to P/E cycles prior to subjecting the memory blocks of the set of memory blocks to P/E cycles.

10. The method of claim 1, wherein the step of performing the integrity checks comprises using ECC mechanisms to generate a checksum of a data range in the wear indicator means and comparing the checksum to subsequent reads of checksums of the same data range.

11. The method of claim 1, wherein the step of taking corrective action comprises at least one of the following actions:

generating a warning;

initiating media scrubbing; and

initiating a data back-up procedure.

12. The method of claim 1, wherein a corrective action is not taken if the bit error rate of the wear indicator means does not correspond to an increased number of P/E cycles.

13. The method of claim 1, further comprising the step of analyzing failure patterns over consecutive P/E cycles of the wear indicator means.

14. The method of claim 13, wherein the analyzing step identifies whether the failure patterns are recurrent during the consecutive P/E cycles.

15. The method of claim 14, wherein the analyzing step averages error rates occurring in the wear indicator means over the consecutive P/E cycles to establish a trend.

16. The method of claim 15, wherein the analyzing step comprises triggering a corrective action if consecutive increases occur in consecutive averaged error rates in the wear indicator means.

17. The method of claim 1, further comprising the step of creating from the memory blocks of the at least one nonvolatile memory device a pool of the first of the memory blocks as part of a modified bad-block management algorithm.

18. A method for predicting failure of a solid-state mass storage device having a controller and NAND flash memory devices that comprise pages organized into memory blocks, the method comprising:

creating from the memory blocks of the NAND flash memory devices a pool of first memory blocks as part of a modified bad-block management algorithm;

assigning the first memory blocks as wear-indicator blocks and excluding the wear-indicator blocks from use as data storage for the NAND flash memory devices;

using from the memory blocks of the NAND flash memory devices a plurality of second memory blocks for data storage whereby data are written to and erased from each of the second memory blocks in program/erase (P/E) cycles;

using information regarding the number of P/E cycles encountered by the second memory blocks to perform wear leveling on the second memory blocks;

using the information to subject the wear-indicator blocks to P/E cycles so that the wear-indicator blocks are subjected to a number of P/E cycles that is greater than the number of P/E cycles encountered by each of the second memory blocks;

performing integrity checks of the wear-indicator blocks and monitoring bit error rates thereof; and

generating a warning of a potential failure of the solid-state mass storage device if the bit error rate of any of the wear-indicator blocks increases.

19. The method of claim 18, further comprising collecting the information regarding the number of P/E cycles encountered by the second memory blocks.