Methods and devices to reduce outer code failure rate variability

• US 8,489,979 B2
• Filed: 05/28/2010
• Issued: 07/16/2013
• Est. Priority Date: 05/28/2010
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Rub, Bernardo
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US12/790,126
• Publication Number:
  US 20110296273A1
• Time in Patent Office: 1,145 Days
• Field of Search: 714/810, 714/755, 714/773
• US Class Current: 714/810
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

The variability of outer code failure rate of memory pages of a solid state memory device can be reduced by selectively grouping the pages included in the outer code words. The data in the page groups are encoded into outer code words which are stored in the memory device. Encoding the data of the page groups and storing the encoded data includes intermittently accumulating an outer code parity as the pages are sequentially stored in the memory device according to a particular order. The pages can be randomly selected for the page groups or can be grouped based on predicted or measured failure rate information. In a memory device having multi-level memory cells, predicting the failure rate of a page can be based on whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page.

Claims

1. A method of encoding and storing data in a solid state memory device, comprising:

encoding data into inner code words corresponding to pages of the memory device that are sequentially accessed in a particular order;

selecting pages for page groups that reduce failure rate variability of outer codes of the page groups, each outer code including outer code parity; and

encoding the page groups into the outer codes and storing the encoded page groups in the memory device, wherein encoding the page groups and storing the encoded page groups includes intermittently accumulating the outer code parity for each of the page groups as the pages are sequentially stored in the memory device according to the particular order.

2. The method of claim 1, wherein selecting the pages for the page groups comprises randomly selecting the pages of the page groups.

3. The method of claim 1, wherein selecting the pages for the page groups comprises:

determining failure rates of the pages; and

selecting the pages for the page groups according to the failure rates of the pages.

4. The method of claim 1, wherein selecting the pages for the page groups comprises:

predicting failure rates of the pages; and

selecting the pages for the page groups according to the predicted failure rates of the pages.

5. The method of claim 4, wherein predicting the failure rates of the pages comprises predicting the failure rates according to whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page.

6. The method of claim 1, wherein storing the page groups comprises interleaving pages of first page group encoded using a first outer code with pages of a second page group encoded using a second outer code.

7. The method of claim 1, wherein encoding and storing the page groups and intermittently accumulating the outer code parity comprises:

storing first pages encoded by a first outer code and accumulating first outer code parity information;

after storing the first pages encoded by the first outer code, storing first pages encoded by a second outer code and accumulating second outer code parity information;

after storing the first pages encoded by the second outer code, storing second pages encoded by the first outer code and continuing to accumulate the first outer code parity information; and

after storing the second pages encoded by the first outer code, storing the first outer code parity information.

8. The method of claim 1, wherein first pages selected for a page group encoded by an outer code have a first failure rate and second pages selected for the page group have a second failure rate that is different from the first failure rate.

9. A method of operating a solid state non-volatile memory device having multi-level memory cells configured to store more multiple bits of data, the method comprising:

encoding data into inner code words, the inner code words arranged according to MSB pages comprising most significant bits (MSBs) of the memory cells and LSB pages comprising least significant bits (LSBs) of the memory cells, the MSB and LSB pages sequentially accessed in a particular order;

encoding page groups of MSB pages and LSB pages into outer codes, each page group having a substantially equal number of MSB pages and LSB pages; and

storing the encoded page groups in the memory device, wherein encoding the page groups and storing the encoded page groups includes intermittently accumulating the outer code parity for each of the page groups as the pages are sequentially stored in the memory device according to the particular order.

10. The method of claim 9, wherein encoding the MSB and LSB pages into the outer codes comprises encoding paired MSB and LSB pages into the outer code words, each of the paired MSB and LSB pages stored together in the same physical page of the memory cells.

11. A solid state memory device comprising:

an inner encoder configured to encode data into inner code words arranged according to pages of the memory device, the pages associated with failure rate information;

page grouping circuitry configured to group the pages into page groups to reduce variability in outer code failure, wherein each of the page groups includes a substantially equal number of most significant bit (MSB) pages and least significant bit (LSB) pages;

an outer encoder configured to encode the pages of the page groups into outer codes, the outer encoder including a parity generator configured to intermittently accumulate the outer code parity for each of the page groups as the pages are sequentially stored in the memory device according to the particular order; and

modulator circuitry configured to store the encoded pages in memory cells of the memory device.

12. The device of claim 11, further comprising:

demodulator circuitry configured to read the encoded pages stored in the memory cells; and

a decoder configured to correct errors in the pages read from the memory cells using the outer code words.

13. The device of claim 11, wherein the outer code words span multiple die of the memory cells.

14. The device of claim 11, wherein the page grouping circuitry is configured to randomly select the pages of each page group.

15. The device of claim 11, wherein the page grouping circuitry is configured to group the pages according to failure rates of the pages.

16. The device of claim 11, wherein the page grouping circuitry is configured to group the pages according to distributions of sensed voltages of the memory cells.

17. The device of claim 11, wherein the page grouping circuitry is configured to dynamically group the pages for each of a plurality of write cycles.

18. The device of claim 11, wherein the MSB and LSB pages are stored together in a physical page of the memory cells.

19. The device of claim 11, wherein the page grouping circuitry is configured to select for each page group at least some first pages having a failure rate below a threshold and at least some second pages having a failure rate above a threshold for each page group.