Method of fabricating a device using low temperature anneal processes, a device and design structure

• US 8,490,029 B2
• Filed: 03/15/2012
• Issued: 07/16/2013
• Est. Priority Date: 07/29/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Domenicucci, Anthony G., Kane, Terence L., Narasimha, Shreesh, Nummy, Karen A., Ontalus, Viorel, Wang, Yun-Yu
• Primary Examiner(s): Dinh, Paul
• Application Number:
  US13/421,400
• Publication Number:
  US 20120180010A1
• Time in Patent Office: 488 Days
• Field of Search: 716 50- 56, 716/106, 716110-112, 716132-136, 438/530, 438/540, 438/550, 438/791, 438/799
• US Class Current: 716/51
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

Claims

1. A method in a computer-aided design system for generating a functional design model of a logic NFET device, the method comprising:

generating a functional representation of a gate structure on a wafer;

generating a functional representation of a stress material on the gate structure;

generating a functional representation of a low temperature anneal process in a range of about 550°

C. to about 650°

C. on the stress material;

generating a functional representation of the stress material being stripped from the gate structure; and

generating a functional representation of the gate structure being subjected to an activation anneal after the stress material is stripped by using the computer-aided design system, wherein the activation anneal is at a temperature higher than the low temperature anneal.

2. The method of claim 1, wherein the functional design model comprises a netlist.

3. The method of claim 1, wherein the functional design model resides on storage medium as a data format used for exchange of layout data of integrated circuits.

4. The method of claim 1, wherein the functional design model resides in a programmable gate array.

5. The method of claim 1, wherein the low temperature anneal process is about below 650°

C.

6. The method of claim 1, wherein the stress material is SiN on the gate structure.

7. The method of claim 1, wherein the activation anneal is a high temperature anneal.

8. The method of claim 7, wherein the high temperature anneal is in a range of about 900°

C. to about 1100°

C.

9. The method of claim 1, wherein the activation anneal is performed at a temperature higher than the low temperature anneal process.

10. The method of claim 1, wherein the functional representation of the gate structure includes a spacer and a sidewall formed over a polysilicon material.

11. The method of claim 1, further comprising generating a functional representation of implanting extension regions and doping source and drain regions in a wafer under a portion of the stress material.