Allocating computer processes to processor cores as a function of process utilizations

• US 8,490,103 B1
• Filed: 04/30/2007
• Issued: 07/16/2013
• Est. Priority Date: 04/30/2007
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Belady, Christian L., Vaden, Thomas L.
• Primary Examiner(s): TO, JENNIFER N
• Application Number:
  US11/742,553
• Time in Patent Office: 2,269 Days
• Field of Search: 718/104
• US Class Current: 718/104
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Computer processes are allocated among cores of a multi-core multi-processor system at least in part as a function of utilization histories of the processes.

Claims

1. A computer system comprising:

an operating system instance;

plural multi-core processors, each of said multi-core processors being an integrated circuit with plural processor cores, each of said cores being configured to execute processes assigned by said operating system instance;

a utilization monitor to track respective per-core utilizations of said processor cores by computer processes and to compile a utilization history;

allocation policies to generate a plan specifying how processes are to be allocated to said processor cores at least in part as a function of said utilization history; and

a workload manager to implement said plan, wherein said workload manger allocates said processes to processor cores so that the processes with highest expected per-core utilizations are allocated to respective cores on a first processor while processes with lowest expected per-core utilizations are allocated to respective processor cores on a second processor which is set at a lower-power active state than is said first processor.

2. The computer system as recited in claim 1 wherein said workload manager further allocates said processes to said processor cores so that expected average per-core utilization is distributed as evenly as possible among said processors.

3. The computer system as recited in claim 1 wherein said second processor is set to an idle state while said processes with highest expected per-core utilizations are allocated to respective cores on said first processor.

4. The computer system as recited in claim 1 wherein a maximum variance of expected per-core utilization among same-processor cores among all processors is less than a variance of average per-core utilization across processors.

5. The computer system as recited in claim 1, wherein, for any of said plural processors, if any of said plural processors, if one of its processor cores enters a lower power state, all of its processor cores must enter that power state.

6. A method comprising:

tracking per-core utilization of processor cores by computer processes for plural multi-core processors concurrently executing processes of the same operating system instance, each of said multi-core processors being an integrated circuit with plural processor cores;

compiling a utilization history for said processes; and

allocating said computer processes to said processor cores as a function of said utilization history and allocation policies, and wherein after said allocating a maximum variance of expected per-core utilization among processor cores of the same processor among all processors is less than a variance of average per-core utilization across processors.

7. The method as recited in claim 6 wherein said allocation policies call for maximizing performance irrespective of power consumption, said computer processes being allocated to processor cores so that expected per-core utilization is distributed as evenly as possible among said processors.

8. The method as recited in claim 6 wherein said allocation policies call for packing processes on processors so that at least a first processor of said processors can enter a lower-power state while another processor of said processors operates in a higher-power state.

9. The method as recited in claim 8 wherein said lower-power state is an idle state.

10. The method as recited in claim 9 wherein said lower-power state provides for executing computer processes.

11. A computer product comprising non-transitory computer-readable media encoded with a program of computer-executable instructions configured for, when executed by a processor:

tracking per-core utilization of processor cores by computer processes for plural multi-core processors executing processes of the same operating system instance;

compiling a utilization history for said processes; and

allocating said processes to said processor cores as a function of said utilization history and allocation policies, wherein said program is further configured to allocate said processes so that a maximum variance of expected per-core utilization among same processor cores among all processors is less than a variance of average per-core utilization across processors.

12. The computer product as recited in claim 11 wherein said allocation policies call for maximizing performance irrespective of power consumption, said processes being allocated to processor cores so that expected per-core utilization is distributed as evenly as possible among said processors.

13. The computer product as recited in claim 11 wherein said allocation policies call for packing processes on processors so that at least a first processor of said processors can enter a lower-power state while another processor of said processors operates in a higher-power state.

14. The computer product as recited in claim 13 wherein said lower-power state is an idle state.