Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels

• US 8,490,107 B2
• Filed: 08/08/2011
• Issued: 07/16/2013
• Est. Priority Date: 08/08/2011
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Jalal, Jamshed, Werkheiser, Mark David, Feero, Brett Stanley, Filippo, Michael Alan, Prasadh, Ramamoorthy Guru, Mannava, Phanindra Kumar
• Primary Examiner(s): Puente, Emerson
• Assistant Examiner(s): Lee, Adam
• Application Number:
  US13/137,362
• Publication Number:
  US 20130042249A1
• Time in Patent Office: 708 Days
• Field of Search: None
• US Class Current: 718/104
• CPC Class Codes: H04L 47/70 Admission control; Resource allocation
• CPC Class Codes: H04L 47/805 QOS or priority aware
• CPC Class Codes: H04L 47/821 Prioritising resource allocation or reservation requests

Abstract

An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.

Claims

1. An integrated circuit comprising:

a plurality of transaction sources configured to generate transaction requests; and

request servicing circuitry configured to process said transaction requests using a set of processing resources;

wherein

said transaction requests each have an associated quality of service value within a range of quality of service values;

said request servicing circuitry is configured to map, in accordance with a quality of service mapping configuration, quality of service values within different sub-ranges of said range of quality of service values to different priority levels within a hierarchy of priority levels extending from a lowest level to a highest level; and

said request servicing circuitry is configured to provide a maximum number of said processing resources that can be concurrently allocated to service transaction requests within each level of said hierarchy, wherein

said request servicing circuitry is configured to;

to receive from a requesting transaction source from among said plurality of transaction sources an at least implicit request to allocate one of said set of processing resources for use by said requesting transaction source in processing a transaction associated with said transaction request;

to determine if one of said set of processing resources is available for use by said requesting transaction source;

if one of said set of processing resources is available for use by said requesting transaction source, then to allocate said one or said set of processing resources to said requesting transaction source for use in processing said transaction; and

if none of said set of processing resources is available for use by said requesting transaction source, then to send a retry response to said requesting transaction source;

said requesting transaction source is configured;

to receive from said request servicing circuitry said retry response; and

to respond to said retry response by waiting for a proceed response to be received from said request servicing circuitry before proceeding with said transaction associated with said transaction request; and

said request servicing circuitry is configured;

to track those of said plurality of transaction sources awaiting a proceed response;

to allocate one of said set of processing resources to one of said transaction sources awaiting a proceed response; and

to send a proceed response to said one of said transaction sources awaiting a proceed response.

2. An integrated circuit as claimed in claim 1, wherein said quality of service mapping configuration is programmable for at least some of said quality of service values.

3. An integrated circuit as claimed in claim 1, wherein said maximum number within each level of said hierarchy is a programmable parameter for at least some levels of said hierarchy.

4. An integrated circuit as claimed in claim 1, wherein said maximum number increases monotonically within said hierarchy of priority.

5. An integrated circuit as claimed in claim 1, wherein when one of said processing resources is allocated to a transaction request within a given level of said hierarchy, then a number of resources tracked by said request servicing circuitry as allocated to said given level and any lower levels within said hierarchy is incremented.

6. An integrated circuit as claimed in claim 1, wherein when one of said processing resources ceases to be allocated to a transaction request within a given level of said hierarchy, then a number of resources tracked by said request servicing circuitry as allocated to said given level and any lower levels within said hierarchy is decremented.

7. An integrated circuit as claimed in claim 1, wherein when one of said processing resources is allocated to a transaction request within a given level of said hierarchy, then a number of resources tracked by said request servicing circuitry as allocated to said given level within said hierarchy is alone incremented.

8. An integrated circuit as claimed in claim 1, wherein when one of said processing resources ceases to be allocated to a transaction request within a given level of said hierarchy, then a number of resources tracked by said request servicing circuitry as allocated to said given level within said hierarchy is alone decremented.

9. An integrated circuit as claimed in claim 1, wherein said request servicing circuitry is configured to switch between dynamic allocation of said processing resources among said transaction requests and static allocation of said processing resources among said transaction request using a selection algorithm.

10. An integrated circuit as claimed in claim 9, wherein said selection algorithm is dependent upon a respective priority level associated with each of said plurality of transaction requests.

11. An integrated circuit as claimed in claim 9, wherein said selection algorithm uses a round robin selection among transaction requests awaiting a static allocation that share a priority level.

12. An integrated circuit as claimed in claim 9, wherein said selection algorithm selects between said transaction requests awaiting static allocation that have different priority levels.

13. An integrated circuit as claimed in claim 12, wherein said selection between said transaction requests awaiting static allocation that have different priority levels is dependence upon a starvation ratio.

14. An integrated circuit as claimed in claim 13, wherein said starvation ratio is programmable.

15. An integrated circuitry as claimed in claim 1, wherein said plurality of transaction sources comprises a plurality of processor clusters each comprising a plurality of processor cores.

16. An integrated circuit as claimed in claim 1, wherein said request servicing circuitry comprises a shared cache memory.

17. An integrated circuit as claimed in claim 1, comprising a plurality of said request servicing circuitry each having a set of processing resources for allocation among said plurality of transaction requests.

18. An integrated circuit as claimed in claim 1, wherein said set of processing resources comprises a set of processing slots available to receive said transaction request.

19. An integrated circuit as claimed in claim 1, further comprising interconnect circuitry configured to communicate said transaction requests between said transaction sources and said request servicing circuitry.

20. An integrated circuit as claimed in claim 19, wherein said interconnect circuitry is ring-based interconnect circuitry.

21. An integrated circuit comprising:

a plurality of transaction source means for generating transaction requests; and

request servicing means for processing said transaction requests using a set of processing resource means for processing;

wherein

said transaction requests each have an associated quality of service value within a range of quality of service values;

said request servicing means is configured to map, in accordance with a programmable quality of service mapping configuration, quality of service values within different sub-ranges of said range of quality of service values to different priority levels within a hierarchy of priority levels extending from a lowest level to a highest level; and

said request servicing means is configured to provide a maximum number of said processing resource means that can be concurrently allocated to service transaction requests within each level of said hierarchy, wherein

said request servicing means is configured to;

to receive from a requesting transaction source means from among said plurality of transaction source means an at least implicit request to allocate one of said set of processing resource means for use by said requesting transaction source means in processing a transaction associated with said transaction request;

to determine if one of said set of processing resource means is available for use by said requesting transaction source means;

if one of said set of processing resource means is available for use by said requesting transaction source means, then to allocate said one or said set of processing resource means to said requesting transaction source means for use in processing said transaction; and

if none of said set of processing resource means is available for use said requesting transaction source means, then to send a retry response to said requesting transaction source means;

said requesting transaction source means is configured;

to receive from said request servicing means said retry response; and

to respond to said retry response by waiting for a proceed response to be received from said request servicing means before proceeding with said transaction associated with said transaction request; and

said request servicing means is configured;

to track those of said plurality of transaction source means awaiting a proceed response;

to allocate one of said set of processing resource means to one of said transaction source means awaiting a proceed response; and

to send a proceed response to said one of said n source means awaiting a proceed response.

22. A method of communicating within an integrated circuit comprising the steps of:

generating transaction requests using a plurality of transaction sources; and

processing said transaction requests using a set of processing resources;

wherein

said transaction requests each have an associated quality of service value within a range of quality of service values; and

further comprising the steps of

mapping, in accordance with a programmable quality of service mapping configuration, quality of service values within different sub-ranges of said range of quality of service values to different priority levels within a hierarchy of priority levels extending from a lowest level to a highest level; and

providing a maximum number of said processing resource means that can be concurrently allocated to service transaction requests within each level of said hierarchy,

said request servicing circuitry performs the steps of;

receiving from a requesting transaction source from among said plurality of transaction sources an at least implicit request to allocate one of said set of processing resources for use by said requesting transaction source in processing a transaction associated with said transaction request;

determining if one of said set of processing resources is available for use by said requesting transaction source;

if one of said set of processing resources is available for use by said requesting transaction source then allocating said one or said set of processing resources to said requesting transaction source for use in processing said transaction; and

if none of said set of processing resources is available for use by said requesting transaction source, then sending a retry response to said requesting transaction source;

said requesting transaction source performs the steps of;

receiving from said request servicing circuitry said retry response; and

responding to said retry response by waiting for a proceed response to be received from said request servicing circuitry before proceeding with said transaction associated with said transaction request; and

said request servicing circuitry performs the steps of;

tracking those of said plurality of transaction sources awaiting a proceed response;

allocating one of said set of processing resources to one of said transaction sources awaiting a proceed response; and

sending a proceed response to said one of said transaction sources awaiting a proceed response.