Semiconductor device with electrically floating body

• US 8,492,209 B2
• Filed: 07/12/2012
• Issued: 07/23/2013
• Est. Priority Date: 01/26/2007
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC (Micron Technology, Inc.)
• Original Assignee: Micron Technology, Inc.
• Inventors: Okhonin, Serguei
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US13/547,717
• Publication Number:
  US 20120273888A1
• Time in Patent Office: 376 Days
• Field of Search: 257/347, 257/348, 438/151, 438/149, 438/158, 365/182
• US Class Current: 438/151
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region, and a gate is disposed over a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion.

Claims

1. A method for forming a transistor, comprising:

forming a semiconductor material on an insulator;

forming an insulating layer and a gate over a first portion of the semiconductor material;

forming spacers over a second portion and a third portion of the semiconductor material, wherein the spacers adjoin the insulating layer, and wherein the first portion, second portion, and third portion form a floating body region;

forming a source region by implanting an impurity into a fourth portion of the semiconductor material after forming the spacers, wherein the fourth portion is adjacent the second portion; and

forming a drain region by implanting the impurity into a fifth portion of the semiconductor material after forming the spacers, wherein the fifth portion is adjacent the third portion;

wherein the electrically floating body region extends outside of at least one lateral boundary of the gate at its closest proximity to the gate such that no portion of at least one of the source region and the drain region is disposed directly under the gate.

2. The method of claim 1, wherein the floating body region comprises a first type of electrical characteristic.

3. The method of claim 2, wherein the source region and drain region each comprise a second type of electrical characteristic that is different from the first type of electrical characteristic.

4. The method of claim 3, wherein implanting the impurity into the fourth portion includes implanting to form a lightly doped source region.

5. The method of claim 3, wherein implanting the impurity into the fourth portion includes implanting to form a highly doped source region.

6. The method of claim 3, wherein implanting the impurity into the fourth portion includes implanting to form a source region that includes both a lightly doped source portion and a highly doped source portion.

7. The method of claim 3, wherein implanting the impurity into the fifth portion includes implanting to form a lightly doped drain region.

8. The method of claim 3, wherein implanting the impurity into the fifth portion includes implanting to form a highly doped drain region.

9. The method of claim 3, wherein implanting the impurity into the fifth portion includes implanting to form a drain region that includes both a lightly doped drain portion and a highly doped drain portion.

10. A semiconductor circuit device produced by the method of claim 1.

11. A semiconductor device produced by the method of claim 1, the semiconductor device comprising:

the floating body region configured to be electrically floating;

the gate disposed over the first portion of the floating body region;

the source region adjoining the second portion of the floating body region, wherein the second portion is adjacent the first portion and separates the source region from the first portion; and

the drain region adjoining the third portion of the floating body region, wherein the third portion is adjacent the first portion and separates the drain region from the first portion.