Trench transistor

• US 8,492,226 B2
• Filed: 09/21/2011
• Issued: 07/23/2013
• Est. Priority Date: 09/21/2011
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Mathew, Shajan, Verma, Purakh Raj
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US13/237,969
• Publication Number:
  US 20130069144A1
• Time in Patent Office: 671 Days
• Field of Search: 438/212, 438/268, 438/270, 438/272, 438/589, 257/330, 257/E21.41, 257/E21.418, 257/E21.419
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method of forming a device is disclosed. A substrate defined with a device region is provided. A buried doped region is formed in the substrate in the device region. A gate is formed in a trench in the substrate in the device region. A channel of the device is disposed on a sidewall of the trench. The buried doped region is disposed below the gate. A distance from the buried doped region to the channel is a drift length L_D of the device. A surface doped region is formed adjacent to the gate.

Claims

1. A method of forming a device comprising:

providing a substrate defined with a device region;

forming a buried doped region in the substrate in the device region;

forming a trench having upper and lower portions of different widths in the substrate in the device region;

forming sidewall spacers on sidewalls of the upper portion of the trench, leaving a portion of the upper portion unfilled;

forming a drain connector in the trench;

removing the sidewall spacers, the removal of the sidewall spacer leaves a gap between the sidewalls of the trench and exposes a portion of the drain connector;

forming a gate in the upper portion of the trench in the substrate in the device region, wherein a channel of the device is disposed on a sidewall of the upper portion of the trench, the buried doped region is disposed below the gate, wherein a distance from the buried doped region to the channel is a drift length L_D of the device, wherein forming the gate comprises

forming gate insulator layer on the exposed portion of the drain connector, and

forming gate electrodes on either side of the gate insulators in the upper portion of the trench; and

forming a surface doped region adjacent to the gate.

2. The method of claim 1 wherein the device region is surrounded by device isolation region.

3. The method of claim 2 wherein the device region comprises one or more internal device region, dividing the device region into multiple device sub-regions.

4. The method of claim 3 wherein the device region comprises:

a first device doped well;

a second device doped well, the second device doped well has a depth equals to a channel length L_C of the channel; and

wherein the first device doped well has a depth greater than the second device doped well.

5. The method of claim 4 wherein the first device doped well comprises first polarity type dopants and the second device doped well comprises second polarity type dopants.

6. The method of claim 5 wherein the second device doped well is disposed substantially within the first device doped well.

7. The method of claim 6 wherein forming a gate in the trench comprises

forming the trench in the first and second device doped wells.

8. The method of claim 7 wherein forming the trench comprises:

forming the upper portion of the trench, the upper portion has a depth greater than an interface of the first and second device doped wells, wherein exposed sidewalls of the upper portion is lined with a gate dielectric layer;

lining a protective layer on the gate dielectric layer;

forming sidewall spacers on sidewalls of the upper portion of the trench, leaving a portion of the upper portion unfilled; and

etching the substrate in the first device doped well to form the lower portion of the trench, the sidewall spacers serve as an etching mask.

9. The method of claim 8 wherein forming the drain connector comprises filling the trench with a drain connector layer.

10. The method of claim 9 wherein forming the gate electrodes comprises:

removing the protective layer except the portion which is protected by the gate insulators, the remaining protective layer forms secondary gate insulators;

filling the gap between the sidewalls of the trench with a gate electrode layer;

planarizing the gate electrode layer, wherein a top surface of the gate electrode layer is substantially co-planar with a top surface of the substrate.

11. A method of forming a device comprising:

providing a substrate defined with a device region;

providing first and second device doped wells in the device region, wherein the first device doped well has a depth greater than the second device doped well;

forming a buried doped region in the first device doped well;

forming a trench having upper and lower portions of different widths in the substrate in the device region;

forming sidewall spacers on sidewalls of the upper portion of the trench, leaving a portion of the upper portion unfilled;

forming a drain connector in the trench;

removing the sidewall spacers, the removal of the sidewall spacer leaves a gap between the sidewalls of the trench and exposes a portion of the drain connector;

forming a gate in the upper portion of the trench in the substrate in the device region, wherein a channel of the device is disposed on a sidewall of the upper portion of the trench, the buried doped region is disposed below the gate, wherein a distance from the buried doped region to the channel is a drift length L_D of the device, wherein forming the gate comprises

forming gate insulator layer on the exposed portion of the drain connector, and

forming gate electrodes on either side of the gate insulators in the upper portion of the trench; and

forming a surface doped region adjacent to the gate.

12. The method of claim 11 wherein the second device doped well has a depth equals to a channel length L_C of the channel.

13. The method of claim 12 wherein the second device doped well is disposed substantially within the first device doped well.

14. The method of claim 13 wherein forming a gate in the trench comprises

forming the trench in the first and second device doped wells.

15. The method of claim 14 wherein forming the trench comprises:

forming the upper portion of the trench, the upper portion has a depth greater than an interface of the first and second device doped wells, wherein an exposed sidewall of the upper portion is lined with a gate dielectric layer;

lining a protective layer on the gate dielectric layer;

forming sidewall spacers on sidewalls of the upper portion of the trench, leaving a portion of the upper portion unfilled; and

etching the substrate in the first device doped well to form the lower portion of the trench, the sidewall spacers serve as an etching mask.

16. The method of claim 15 wherein forming the drain connector comprises filling the trench with a drain connector layer.

17. The method of claim 16 wherein forming the gate electrodes comprises:

removing the protective layer except the portion which is protected by the gate insulators, the remaining protective layer forms secondary gate insulators;

filling the gap between the sidewalls of the trench with a gate electrode layer;

planarizing the gate electrode layer, wherein a top surface of the gate electrode layer is substantially co-planar with a top surface of the substrate.

18. A method of forming a device comprising:

providing a substrate defined with a device region;

forming a buried doped region in the substrate in the device region;

forming a first trench in the substrate in the device region;

forming a second trench in the first trench, wherein the second trench has a depth deeper than the first trench;

forming sidewall spacers on sidewalls of the first trench, leaving a portion of the first trench unfilled;

forming a drain connector in the first and second trenches;

removing the sidewall spacers, the removal of the sidewall spacer leaves a gap between the sidewalls of the first trench and exposes a portion of the drain connector in the first trench;

forming a gate in the first trench in the substrate in the device region, wherein a channel of the device is disposed on a sidewall of the first trench, the buried doped region is disposed below the gate, wherein a distance from the buried doped region to the channel is a drift length L_D of the device, wherein forming the gate comprises

forming gate insulator layer on the exposed portion of the drain connector, and

forming gate electrodes on either side of the gate insulators in the first trench; and

forming a surface doped region adjacent to the gate.