Three dimensional integration and methods of through silicon via creation

• US 8,492,252 B2
• Filed: 03/16/2012
• Issued: 07/23/2013
• Est. Priority Date: 01/14/2010
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Farooq, Mukta G., Kinser, Emily R., Wise, Richard, Yusuff, Hakeem
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): BACHNER, ROBERT G
• Application Number:
  US13/422,445
• Publication Number:
  US 20120190196A1
• Time in Patent Office: 494 Days
• Field of Search: 438/525, 438/533, 438/622, 257/E21.586
• US Class Current: 438/525
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure.

Claims

1. A method comprising:

patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer;

forming doped portions on a sacrificial substrate layer of the substrate layer to define an exposed doped portion of the sacrificial substrate layer and an exposed undoped portion of the sacrificial substrate layer;

removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer; and

etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure,

wherein the exposed doped portion is more selective to etching than the exposed undoped portion, and

wherein the etching includes etching the doped portion such that the etching of the first cavity and the etching of the doped portion results in openings of different depths.

2. The method of claim 1, wherein the structure includes a first wafer and a second wafer.

3. The method of claim 1, wherein the structure includes a first chip and a second chip.

4. The method of claim 1, wherein the method further comprises:

removing the remaining photoresist layer;

forming a dielectric portion in the cavities;

removing a portion of the dielectric layer;

depositing a barrier layer on the dielectric layer;

filling the cavities with a conductive material; and

removing the excess conductive material by planarization.

5. The method of claim 1, wherein the conductive material is operative to electrically connect the first conductor to the second conductor.

6. The method of claim 1, wherein the forming doped portions further includes implanting ions in a planar region of the sacrificial substrate layer to define the exposed doped portion and the exposed undoped portion.