Method of forming E-fuse in replacement metal gate manufacturing process

• US 8,492,286 B2
• Filed: 11/22/2010
• Issued: 07/23/2013
• Est. Priority Date: 11/22/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Utomo, Henry K., Li, Ying, Leake, Gerald L.
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US12/951,107
• Publication Number:
  US 20120129312A1
• Time in Patent Office: 974 Days
• Field of Search: 438/381, 438/712, 438/721, 438/755, 257/377, 257/413
• US Class Current: 438/712
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Embodiment of the present invention provides a method of forming electronic fuse or commonly known as e-fuse. The method includes forming a polysilicon structure and a field-effect-transistor (FET) structure together on top of a common semiconductor substrate, the FET structure having a sacrificial gate electrode; implanting at least one dopant into the polysilicon structure to create a doped polysilicon layer in at least a top portion of the polysilicon structure; subjecting the polysilicon structure and the FET structure to a reactive-ion-etching (RIE) process, the RIE process selectively removing the sacrificial gate electrode of the FET structure while the doped polysilicon layer being substantially unaffected by the RIE process; and converting the polysilicon structure including the doped polysilicon layer into a silicide to form the electronic fuse.

Claims

1. A method of forming an electronic fuse comprising:

forming a polysilicon structure on top of a semiconductor substrate;

implanting at least one dopant into said polysilicon structure to create a doped polysilicon layer in at least a top portion of said polysilicon structure;

subjecting said doped polysilicon layer to a reactive-ion-etching (RIE) process, said doped polysilicon layer being substantially unaffected by said RIE process; and

converting said polysilicon structure including said doped polysilicon layer into a silicide to form said electronic fuse,

wherein subjecting said doped polysilicon layer to said RIE process further comprises removing a cap layer on top of a sacrificial gate electrode of a transistor, wherein said transistor is formed on said semiconductor substrate thereupon said polysilicon structure is formed and wherein said removing removes, at most, a fraction of said doped polysilicon layer with rest of said doped polysilicon layer covering rest of said polysilicon structure, and subsequently applying said RIE process in removing selectively said sacrificial gate electrode of said transistor.

2. The method of claim 1, wherein said at least one dopant is boron (B).

3. The method of claim 2, further comprising, before performing said RIE process, performing a rapid thermal annealing (RTA) process to activate said boron dopant being implanted.

4. The method of claim 1, wherein said polysilicon structure is insulated from said semiconductor substrate by a dielectric layer formed directly underneath said polysilicon structure, and has dielectric spacers formed at sidewalls thereof.

5. The method of claim 1, wherein converting said polysilicon structure into said silicide further comprises:

forming a hard mask pattern, said hard mask pattern covering said transistor but exposing said doped polysilicon layer and said polysilicon structure underneath;

depositing a metal layer in direct contact with said doped polysilicon layer; and

causing diffusion, through a rapid thermal annealing process, of said metal layer into at least said doped polysilicon layer to create said silicide.

6. The method of claim 5, wherein said metal layer is a layer of nickel, further comprising causing diffusion of said nickel into said polysilicon structure underneath said doped polysilicon layer.

7. The method of claim 1, wherein said doped polysilicon layer is not etched by said RIE process.

8. The method of claim 1, wherein said implanting converts entire said polysilicon structure into said doped polysilicon layer.

9. A method comprising:

forming a polysilicon structure and a field-effect-transistor (FET) structure together on top of a common semiconductor substrate, said FET structure having a sacrificial gate electrode;

implanting at least one dopant into said polysilicon structure to create a doped polysilicon layer in at least a top portion of said polysilicon structure;

subjecting said polysilicon structure and said FET structure to a reactive-ion-etching (RIE) process, said RIE process selectively removing said sacrificial gate electrode of said FET structure while said doped polysilicon layer being substantially unaffected by said RIE process; and

converting said polysilicon structure including said doped polysilicon layer into a silicide to form said electronic fuse,

wherein converting said polysilicon structure into said silicide further comprises;

forming a hard mask pattern, said hard mask pattern covering said FET structure but exposing said doped polysilicon layer and said polysilicon structure underneath;

depositing a metal layer in direct contact with said doped polysilicon layer; and

causing diffusion, through a rapid thermal annealing process, of said metal layer into at least said doped polysilicon layer to create said silicide.

10. The method of claim 9, wherein said at least one dopant is boron (B), said boron being implanted into said polysilicon structure while said FET structure is protected from said boron implantation, by a photo-resist mask.

11. The method of claim 10, further comprising, after said boron implantation, performing a rapid thermal annealing (RTA) process to activate said boron dopant such that said doped polysilicon layer being resistant to said RIE process.

12. The method of claim 9, further comprising, before performing said RIE process, removing a cap layer on top of said sacrificial gate electrode of said FET structure, wherein said removing also removes, at most, a fraction of said doped polysilicon layer with rest of said doped polysilicon layer covering rest of said polysilicon structure.

13. The method of claim 9, wherein said metal layer is a layer of nickel, further comprising causing said nickel diffuse into said polysilicon structure underneath said doped polysilicon layer.

14. A method comprising:

forming an electronic fuse (e-fuse) structure and a field-effect-transistor (FET) structure on top of a semiconductor substrate, said e-fuse structure including a polysilicon layer and said FET structure having a sacrificial gate electrode;

implanting a boron (B) dopant into said polysilicon layer of said e-fuse structure to create a doped polysilicon layer in at least a top portion thereof;

removing a cap layer on top of said sacrificial gate electrode of said FET structure, wherein said removing also removes a fraction of said doped polysilicon layer with rest of said doped polysilicon layer covering rest of said e-fuse structure;

subjecting said e-fuse structure and said FET structure to a common reactive-ion-etching (RIE) process, said RIE process selectively removing said sacrificial gate electrode of said FET structure while causing no substantial changes to said e-fuse structure; and

performing silicidation of said doped polysilicon layer to convert said e-fuse structure into an e-fuse.

15. The method of claim 14, wherein said implanting converts said e-fuse structure entirely into said doped polysilicon layer.

16. The method of claim 14, wherein during said implanting, said FET structure is covered by a photo-resist mask, said photo-resist mask preventing said FET structure from being implanted by said boron dopant.