Non-volatile semiconductor memory device and manufacturing method thereof

• US 8,492,826 B2
• Filed: 05/18/2010
• Issued: 07/23/2013
• Est. Priority Date: 10/09/2007
• Status: Expired due to Fees

• Current Assignee: Genusion, Inc.
• Original Assignee: Genusion, Inc.
• Inventors: Ajika, Natsuo, Shukuri, Shoji, Shimizu, Satoshi, Ogura, Taku
• Primary Examiner(s): Coleman, William D
• Assistant Examiner(s): ENAD, CHRISTINE A
• Application Number:
  US12/782,378
• Publication Number:
  US 20100283099A1
• Time in Patent Office: 1,162 Days
• Field of Search: 257/314, 257/324, 257/E29.279, 257/E29.224, 257/246
• US Class Current: 257/324
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

Claims

1. A non-volatile semiconductor device having a memory cell formed on an n type well formed in a semiconductor substrate, comprising:

a first p-type diffusion region formed on a surface of the n type well;

a second p-type diffusion region formed on the surface of the n type well, a channel region being interposed between the first p-type diffusion region and the second p-type diffusion region;

a tunnel insulation film formed on the channel region;

a floating gate formed on the tunnel insulation film;

an insulation film formed on the floating gate;

a gate electrode formed on the insulation film; and

a metal wire connected to the first p-type diffusion region, the metal wire intersecting with an extension of the gate electrode;

wherein the first p-type diffusion region and the second p-type diffusion region are asymmetrically arranged such that (i) a junction depth of the first p-type diffusion region and a junction depth of the second p-type diffusion region are different;

or (ii) a first shape of the first p-type diffusion region and a second shape of the second p-type diffusion region are different; and

such that a first resistivity of the first p-type diffusion region is lower than a second resistivity of the second p-type diffusion region; and

wherein the device is configured such that a gate read voltage Vgr is applied to the gate electrode when the memory cell is selected for reading during a read operation, and an unselected gate read voltage uVgr is applied to the gate electrode when the memory cell is not selected for the reading during the read operation, and Vgr is lower than uVgr.

2. The non-volatile semiconductor device according to claim 1, wherein a negative erase voltage Vge is applied to the gate electrode when the memory cell is erased.

3. The non-volatile semiconductor device according to claim 1, wherein a positive gate program voltage Vgp is applied to the gate electrode when the memory cell is selected for programming during a program operation, and a zero or positive gate program voltage uVgp is applied to the gate electrode when the memory cell is not selected for the programming during the program operation, wherein Vpg is higher than uVpg.

4. The non-volatile semiconductor device according to claim 1 wherein:

when the memory cell is selected for programming during a program operation, a first program voltage Vdp is applied to the first p-type diffusion region and a second program voltage Vsp is applied to the second p-type diffusion region, Vsp being higher than Vdp; and

when the memory cell is selected for reading during the read operation, a first read voltage Vdr is applied to the first p-type diffusion region and a second read voltage Vsr is applied to the second p-type diffusion region, Vdr being higher than Vsr.

5. A non-volatile semiconductor device having a memory cell formed on an n type well formed in a semiconductor substrate, comprising:

a first p-type diffusion region formed on a surface of the n type well;

a second p-type diffusion region formed on the surface of the n type well, a channel region being interposed between the first p-type diffusion region and the second p-type diffusion region;

a tunnel insulation film formed on the channel region;

a floating gate formed on the tunnel insulation film;

an insulation film formed on the floating gate; and

a gate electrode formed on the insulation film;

wherein the first p-type diffusion region and the second p-type diffusion region are asymmetrically arranged such that (i) a junction depth of the first p-type diffusion region and a junction depth of the second p-type diffusion region are different;

or (ii) a first shape of the first p-type diffusion region and a second shape of the second p-type diffusion region are different; and

such that a first resistivity of the first p-type diffusion region is lower than a second resistivity of the second p-type diffusion region; and

wherein a first program voltage Vdp is applied to the first p-type diffusion region, a second program voltage Vsp is applied to the second p-type diffusion region, a third program voltage Vgp is applied to the gate electrode and a fourth program voltage Vbp is applied to the n-type well when the memory cell is selected for programming during a program operation, the first to fourth program voltages having values as follows;

Vgp≧

Vbp>

Vsp≧

Vdp; and

wherein a first read voltage Vdr is applied to the first p-type diffusion region, a second read voltage Vsr is applied to the second p-type diffusion region, a third read voltage Vgr is applied to the gate electrode and the a fourth read voltage Vbr is applied to the n-type well when the memory cell is selected for reading during a read operation, the first to fourth read voltages having values as follows;

Vbr≧

Vdr>

Vsr≧

Vgr.

6. The non-volatile semiconductor device according to claim 5, wherein a first standby voltage Vdsb is applied to the first p-type diffusion region, a second standby voltage Vssb is applied to the second p-type diffusion region, a third standby voltage Vgsb is applied to the gate electrode and a fourth standby voltage Vbsb is applied to the n-type well when the memory cell is at a standby operation, the first to fourth standby voltages having values as follows:

Vgsb=Vbsb>

Vssb=Vdsb.

7. The non-volatile semiconductor device according to claim 6, wherein Vgsb=Vbsb=Vcc and Vssb=Vdsb=0V.