Reduced process sensitivity of electrode-semiconductor rectifiers

• US 8,492,837 B2
• Filed: 10/27/2011
• Issued: 07/23/2013
• Est. Priority Date: 06/12/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Rinehimer, Mark L., Grebs, Thomas E., Benjamin, John L.
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US13/283,496
• Publication Number:
  US 20120037982A1
• Time in Patent Office: 635 Days
• Field of Search: 257/335, 257/341, 257/E21.345, 257/E21.41, 257/E29.013, 438/87
• US Class Current: 257/341
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

Claims

1. A semiconductor device, comprising:

a semiconductor layer;

a trench disposed in the semiconductor layer;

a first electrode disposed in the trench;

a mesa region adjacent to the trench and being defined, at least in part, by the trench, the mesa region having a top surface and a graded region, the graded region having a doping concentration decreasing with increasing depth from the top surface of the mesa region, the doping concentration of the graded region being highest at the top surface of the mesa region, the first electrode having at least a portion electrically insulated from the mesa region; and

a second electrode disposed on the top surface of the mesa region, the second electrode being a first portion of a Schottky contact, the top surface of the mesa region being a second portion of the Schottky contact.

2. The semiconductor device of claim 1, wherein the graded region has a depth of at least a quarter-micron from the top surface of the mesa region.

3. The semiconductor device of claim 1, wherein a portion of the mesa region located below the graded region has a doping concentration that increases with increasing depth from the top surface of the mesa region.

4. The semiconductor device of claim 1, wherein the mesa region has a portion disposed between the graded region and a third electrode, the doping concentration of the portion of the mesa region increasing with increasing depth from the top surface of the mesa region.

5. The semiconductor device of claim 1, wherein the first electrode has at least one side wall and a bottom wall,

the semiconductor device further comprising:

an enhanced doping region disposed in the semiconductor layer and having a net doping concentration that is greater than a maximum value of a doping concentration of the mesa region, the enhanced doping region being disposed adjacent to the bottom wall of the trench.

6. The semiconductor device of claim 5, wherein the net doping concentration of the enhanced doping region is greater than the maximum value of the doping concentration of the mesa region by at least an amount of 2×

10¹⁶ cm<sup>−

3</sup>.

7. The semiconductor device of claim 1, wherein the graded region has a maximum doping concentration and a minimum doping concentration, a ratio of the maximum doping concentration to the minimum doping concentration is equal to or greater than two.

8. The semiconductor device of claim of claim 1, wherein a maximum doping concentration in the mesa region is equal to or less than 2×

10¹⁷ cm<sup>−

3</sup>.

9. The semiconductor device of claim 1, wherein the graded region has a maximum doping concentration equal to or less than 8×

10¹⁶ cm<sup>−

3</sup>.

10. The semiconductor device of claim 1, wherein a top surface of the first electrode is in contact with the second electrode.

11. The semiconductor device of claim 1, wherein the graded region has a depth of less than one-half of a height of the mesa region.

12. The semiconductor device of claim 1, further comprising a dielectric insulating the first electrode from the mesa region, the second electrode having a first portion disposed on the top surface of the mesa region and a second portion disposed on a top surface of the first electrode, the first portion of the second electrode being electrically insulated from at least a portion of the second portion of the second electrode by the dielectric.

13. A method of making a semiconductor device, comprising:

forming a mesa region of semiconductor material in a semiconductor layer, the mesa region having a top surface;

forming a graded region of the mesa region having a doping concentration decreasing with increasing depth from the top surface of the mesa region, the doping concentration of the graded region being highest at the top surface of the mesa region, the graded region having a same net conductivity type as the semiconductor layer; and

forming a contact electrode on the top surface of the mesa region, the contact electrode being a first portion of a Schottky contact, the top surface of the mesa region being a second portion of the Schottky contact.

14. The method of claim 13, the method further comprising:

forming a trench in the semiconductor layer to define the mesa region.

15. The method of claim 13, wherein the forming of the mesa region includes implanting a boron dopant at an energy of at least 70 KeV.

16. The method of claim 13, wherein the forming of the mesa region includes implanting a dopant at an energy of 40 KeV or less.

17. The method of claim 13, wherein the graded region has a depth of less than one-half micron.

18. The method of claim 13, wherein the contact electrode is a silicide layer.

19. A semiconductor device, comprising:

a semiconductor layer;

a mesa region disposed in the semiconductor layer, the mesa region having a top surface and a graded region, the graded region having a doping concentration decreasing with increasing depth from the top surface of the mesa region, the doping concentration of the graded region being highest at the top surface of the mesa region, the graded region having a same net conductivity type as the semiconductor layer;

a first electrode disposed in a trench within the semiconductor layer;

a dielectric disposed in the trench and insulating the mesa region from the first electrode; and

a second electrode having a portion disposed on the mesa region, the portion being a portion of a Schottky contact with the top surface of the mesa region.

20. The semiconductor device of claim 19, wherein the graded region has a maximum doping concentration and a minimum doping concentration, a ratio of the maximum doping concentration to the minimum doping concentration is equal to or greater than two.

21. The semiconductor device of claim 19, wherein the portion is a first portion, the second electrode has a second portion disposed on the first electrode.

22. The semiconductor device of claim 19, wherein the portion is a first portion, the second electrode has a second portion disposed on the mesa region, the second portion of the second electrode is insulated from at least a portion of the first electrode by the dielectric.