Same-chip multicharacteristic semiconductor structures

• US 8,492,839 B2
• Filed: 08/24/2010
• Issued: 07/23/2013
• Est. Priority Date: 08/24/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Cheng, Kangguo, Khakifirooz, Ali, Kulkarni, Pranita, Shahidi, Ghavam G.
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US12/861,976
• Publication Number:
  US 20120049284A1
• Time in Patent Office: 1,064 Days
• Field of Search: 257/347, 257/351, 257/E27.112
• US Class Current: 257/347
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.

Claims

1. A method comprising:

providing a semiconductor-on-insulator substrate comprised of a top semiconductor layer overlying an insulation layer, where the insulation layer overlies a bottom silicon layer, where the top semiconductor layer has a first thickness, a first width and a first depth, where the top semiconductor layer comprises a first portion and a second portion;

removing part of the second portion of the top semiconductor layer to achieve at least one of a second width that is less than the first width, and a second depth that is less than the first depth, where the removed part of the second portion is less than an entirety of the second portion;

disposing a first insulator on the first portion of the top semiconductor layer and a second insulator on the second portion of the top semiconductor layer, where a total thickness of the first portion substantially equals a total thickness of the second portion;

forming at least one first device that at least partially overlies and is disposed upon the first insulator and the first portion of the top silicon layer; and

forming at least one second device that at least partially overlies and is disposed upon the second insulator and the second portion of the top silicon layer.

2. The method of claim 1, where the at least one first device comprises at least one first transistor and the at least one second device comprises at least one second transistor, where the at least one first transistor comprises a first spacer having a first spacer thickness, where the at least one second transistor comprises a second spacer having the first spacer thickness, the method further comprising:

thinning the second spacer to achieve a second spacer thickness that is less than the first spacer thickness.

3. The method of claim 1, further comprising:

forming at least one raised source/drain structure coupled to at least one of the at least one first device and the at least one second device.

4. The method of claim 1, further comprising:

forming at least one isolation structure that separates the first portion from the second portion.

5. The method of claim 1, where the semiconductor-on-insulator substrate comprises an extremely thin silicon-on-insulator.

6. The method of claim 1, where a difference between at least one of the first width and the second width and the first depth and second depth is about 5% to about 35%.

7. The method of claim 1, where the removal of part of the second portion of the top semiconductor layer achieves a second width that is less than the first width.

8. The method of claim 1, where the removal of part of the second portion of the top semiconductor layer achieves a second depth that is less than the first depth.

9. A method comprising:

providing an extremely thin semiconductor-on-insulator substrate;

disposing a first insulator on a first portion of the substrate and a second insulator on a second portion of the substrate, where a total thickness of the first portion substantially equals a total thickness of the second portion;

forming at least one first device that at least partially overlies the substrate and is disposed on the first insulator and the first portion of the substrate, where the at least one first device comprises a first transistor with a first spacer having a first spacer thickness;

forming at least one second device that at least partially overlies the substrate and is disposed on the second insulator and the second portion of the substrate, where the at least one second device comprises a second transistor with a second spacer having a second spacer thickness; and

thinning the second spacer to reduce the second spacer thickness such that the first spacer thickness is greater than the second spacer thickness, where the first spacer thickness is about 7.5 nm and the thinned second spacer thickness is about 6 nm.

10. The method of claim 9, where the at least one first device comprises at least one first field effect transistor and the at least one second device comprises at least one second field effect transistor.

11. The method of claim 9, further comprising:

forming at least one raised source/drain structure coupled to at least one of the at least one first device and the at least one second device.

12. The method of claim 9, where a difference in thickness between the first spacer thickness and the second spacer thickness is about 5% to about 35%.

13. A method comprising:

providing a semiconductor-on-insulator substrate comprised of a top semiconductor layer overlying an insulation layer, where the insulation layer overlies a bottom silicon layer, where the top semiconductor layer has a first thickness, a first width and a first depth, where the top semiconductor layer comprises a first portion and a second portion;

removing part of the second portion of the top semiconductor layer to achieve a second thickness that is less than the first thickness, where the removed part of the second portion is less than an entirety of the second portion;

disposing a first insulator on the first portion of the top semiconductor layer and a second insulator on the second portion of the top semiconductor layer, where a total thickness of the first portion substantially equals a total thickness of the second portion;

forming at least one first device that at least partially overlies and is disposed upon the first insulator and the first portion of the top silicon layer; and

forming at least one second device that at least partially overlies and is disposed upon the second insulator and the second portion of the top silicon layer.

14. The method of claim 13, where a difference in thickness between the first thickness and the second thickness is about a 35% difference.

15. The method of claim 13, where a difference in thickness between the first thickness and the second thickness is in a range of 20% difference to 35% difference.

16. The method of claim 13, where the first thickness is about 10 nm and the second thickness is about 5 nm.

17. The method of claim 13, where the first thickness is about 8 nm and the second thickness is about 5 nm.

18. A method comprising:

providing a semiconductor-on-insulator substrate comprised of a top semiconductor layer overlying an insulation layer, where the insulation layer overlies a bottom silicon layer, where the top semiconductor layer has a first thickness, a first width and a first depth, where the top semiconductor layer comprises a first portion and a second portion;

removing part of the second portion of the top semiconductor layer to achieve;

a second thickness that is less than the first thickness, a second width that is less than the first width, and a second depth that is less than the first depth, where the removed part of the second portion is less than an entirety of the second portion;

disposing a first insulator on the first portion of the top semiconductor layer and a second insulator on the second portion of the top semiconductor layer, where a total thickness of the first portion substantially equals a total thickness of the second portion;

forming at least one first device that at least partially overlies and is disposed upon the first insulator and the first portion of the top silicon layer; and

forming at least one second device that at least partially overlies and is disposed upon the second insulator and the second portion of the top silicon layer.