Stress-generating shallow trench isolation structure having dual composition

• US 8,492,846 B2
• Filed: 11/15/2007
• Issued: 07/23/2013
• Est. Priority Date: 11/15/2007
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Zhu, Huilong, Wang, Jing
• Primary Examiner(s): Lam, Cathy N
• Application Number:
  US11/940,531
• Publication Number:
  US 20090127626A1
• Time in Patent Office: 2,077 Days
• Field of Search: 257/369, 257/374, 257/274, 257/278, 257/368, 257/E23.002, 257/E27.66, 257/E21.546, 257/351, 257/352, 257506-510, 438/424, 438/279, 438/299, 438/301
• US Class Current: 257/369
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.

Claims

1. A semiconductor structure comprising:

an active area comprising a semiconductor material and located in a semiconductor substrate;

a first shallow trench isolation portion laterally abutting lengthwise sidewalls of a only middle portion of said active area; and

a set of two second shallow trench isolation portions, each laterally abutting remaining lengthwise sidewalls of said active area as well as widthwise sidewalls of end portions of said active area, wherein said first shallow trench isolation portion and said set of two second shallow trench isolation portions comprise different materials, and wherein one of said set of two second shallow trench isolation portions is in direct contact with a first sidewall of said first shallow trench isolation portion and another of said set of two second shallow trench isolation portions is in direct contact with a second sidewall of said first shallow trench isolation portion, said second sidewall of said first shallow trench isolation portion is opposite of said first sidewall of said first shallow trench isolation portion.

2. The semiconductor structure of claim 1, wherein said first shallow trench isolation portion applies a first type of stress to said lengthwise sidewalls of said middle portion of said active area, and wherein each of said second shallow trench isolation portions applies a second type of stress to said lengthwise sidewalls and said widthwise sidewalls of said end portions of said active area, and wherein one of said first and second stress types is compressive and the other of said first and second stress types is tensile.

3. The semiconductor structure of claim 1, wherein said first shallow trench isolation portion or said set of two second shallow trench isolation portions comprises a stress-generating material that applies a stress to said active area to affect charge carrier mobility of said active area, and wherein the first shallow trench isolation portion or said set of two second shallow trench isolation portions not including the stress-generating material comprises a non-stress-generating material that does not generate a sufficient stress to affect charge carrier mobility.

4. The semiconductor structure of claim 3, wherein said stress-generating material is one of a tensile-stress-generating silicon nitride and a compressive-stress-generating silicon nitride, and wherein said non-stress-generating material comprises one of undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), fluorosilicate glass (FSG), and borophosphosilicate glass (BPSG).

5. The semiconductor structure of claim 1, wherein said first shallow trench isolation portion comprises a tensile-stress-generating material and said set of two second shallow trench isolation portions comprise a compressive-stress-generating material.

6. The semiconductor structure of claim 5, wherein said tensile-stress-generating material is a tensile-stress-generating silicon nitride, and wherein said compressive-stress-generating material is a compressive-stress-generating silicon nitride.

7. The semiconductor structure of claim 1, wherein said first shallow trench isolation portion comprises a compressive-stress-generating material and said set of two second shallow trench isolation portions comprise a tensile-stress-generating material.

8. The semiconductor structure of claim 1, further comprising:

a gate dielectric and a gate electrode located on said active area; and

a channel located in said active area and vertically abutting said gate dielectric, wherein said first shallow trench isolation portion and said set of two second shallow trench isolation portions apply a longitudinal stress along a lengthwise direction in said channel and a transverse stress along a widthwise direction of said channel, wherein one of said longitudinal stress and said transverse stress is compressive, and wherein an other of said longitudinal stress and said transverse stress is tensile.

9. The semiconductor structure of claim 7, wherein said tensile-stress-generating material is a tensile-stress-generating silicon nitride, and wherein said compressive-stress-generating material is a compressive-stress-generating silicon nitride.

10. The semiconductor structure of claim 1, wherein said active area is single crystalline.

11. The semiconductor structure of claim 1, wherein said active area is a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate.

12. The semiconductor structure of claim 1, wherein said active area is a portion of a bulk substrate.

13. The semiconductor structure of claim 1, wherein said first shallow trench isolation portion and each of said second shallow trench isolation portions have substantially the same depth.