Semiconductor package with interconnect layers

• US 8,492,870 B2
• Filed: 06/13/2011
• Issued: 07/23/2013
• Est. Priority Date: 01/19/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US13/159,190
• Publication Number:
  US 20110309473A1
• Time in Patent Office: 771 Days
• Field of Search: None
• US Class Current: 257/516
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A chip package comprising a glass substrate, wherein a first opening in the glass substrate passes vertically through the glass substrate, a semiconductor chip, a wiring structure comprising a first portion in the first opening and a second portion over the glass substrate, wherein the first portion is connected to the semiconductor chip, wherein the wiring structure comprises a passive device, wherein the wiring structure comprises copper, and a dielectric layer over the glass substrate and on the wiring structure, wherein a second opening in the dielectric layer is over a contact point of the wiring structure, and the contact point is at a bottom of the second opening.

Claims

1. A chip package comprising:

an etchable glass substrate, wherein a first opening in said etchable glass substrate passes through said etchable glass substrate;

a semiconductor chip coupled to the etchable glass substrate;

a conductive structure comprising a first portion disposed within said first opening and a second portion coupled to the etchable glass substrate, wherein said first portion is coupled to said semiconductor chip, wherein said conductive structure comprises a passive device; and

a dielectric layer over said etchable glass substrate and over said conductive structure, wherein a second opening in said dielectric layer exposes a contact point of said conductive structure.

2. The chip package of claim 1, wherein said passive device comprises an inductor.

3. The chip package of claim 1, wherein said passive device comprises a capacitor.

4. The chip package of claim 1, wherein said passive device comprises a resistor.

5. The chip package of claim 1, wherein said first opening is aligned with said semiconductor chip.

6. The chip package of claim 1, wherein said semiconductor chip is at a bottom side of said etchable glass substrate.

7. The chip package of claim 1 further comprises a conductive interconnect over said etchable glass substrate, wherein said conductive interconnect is coupled to said semiconductor chip.

8. The chip package of claim 7, wherein said conductive interconnect comprises a gold interconnect.

9. The chip package of claim 7, wherein said conductive interconnect comprises a solder interconnect.

10. The chip package of claim 1, wherein said etchable glass substrate has a width greater than that of said semiconductor chip.

11. The chip package of claim 1, wherein said dielectric layer comprises a polymer layer.

12. The chip package of claim 1, wherein said semiconductor chip is coupled with said etchable glass substrate.

13. The chip package of claim 1, wherein said semiconductor chip joins said conductive structure.

14. The chip package of claim 1, wherein said conductive structure comprises electroplated copper.