3D integrated circuit with logic

• US 8,492,886 B2
• Filed: 11/22/2010
• Issued: 07/23/2013
• Est. Priority Date: 02/16/2010
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Wurman, Ze'ev
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US12/951,924
• Publication Number:
  US 20120196390A1
• Time in Patent Office: 974 Days
• Field of Search: 257686-778, 257/E23.085
• US Class Current: 257/686
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/302 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/8232 Field-effect technology
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/29599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/4827 : Materials
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/11807 : CMOS gate arrays
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

An integrated circuit including a first layer of logic circuits, and a second layer of logic circuits overlaying the first layer, wherein the first layer includes a multiplicity of flip-flops wherein each of the flip-flops has at least one connection to the second layer, and wherein the second layer includes at least one logic circuit with inputs including the connection and with at least one output connected to the first layer.

Claims

1. An integrated circuit comprising:

a first layer of logic circuits, and

a second layer of logic circuits overlaying said first layer, wherein said first layer comprises a multiplicity of flip-flops wherein each of said flip-flops has at least one connection to said second layer, and wherein

said second layer comprises at least one logic circuit with inputs comprising said connection and with at least one output connected to said first layer.

2. A circuit according to claim 1 wherein said at least one logic circuit overlays a said first layer logic circuit and wherein said first layer logic circuit is substantially the same as said at least one logic circuit.

3. A circuit according to claim 1 wherein said first layer comprises a selector to select between said output and a signal generated within said first layer.

4. A circuit according to claim 3, further comprising a controller adapted to perform testing of said first layer logic circuits and control said selector.

5. A circuit according to claim 2, further comprising a comparator to compare said output to a signal generated by said first layer logic circuit.

6. A circuit according to claim 3, further comprising a Built-In-Self-Test (BIST) circuit.

7. A circuit according to claim 3 wherein the output of said selector is an input to at least one of first layer said flip-flops.

8. A circuit according to claim 1 wherein said second layer is substantially the same as said first layer.

9. An integrated circuit according to claim 3, wherein

said first layer comprises a combinatorial function with function inputs and one function output, and wherein

said function inputs are connected to said at least one connection and said signal is connected to said function output.

10. An integrated circuit comprising:

a first layer of logic circuits, and

a second layer of logic circuits overlaying said first layer,

wherein said first layer comprises a multiplicity of logic-cones,

wherein each of said logic-cones has a multiplicity of cone-inputs,

wherein each of said cone-inputs is an output of a flip-flop,

wherein each of said logic-cones has a multiplicity of logic gates forming a combinatorial function of said cone-inputs, wherein said function has a cone-output,

wherein said second layer comprises at least one logic circuit,

wherein at least one of said logic-cones has a cone-input connected to said at least one logic circuit, and

wherein said at least one logic circuit has a circuit-output which is connected to said first layer.

11. A circuit according to claim 10 wherein said at least one logic circuit overlays said at least one of said logic-cones.

12. A circuit according to claim 10 wherein said at least one logic circuit is substantially the same as said at least one of said logic-cones.

13. A circuit according to claim 10 wherein said first layer comprises a selector to select between said circuit-output and a cone-output of said at least one of said logic-cones.

14. A circuit according to claim 13, further comprising a controller which is adapted to perform testing of said first layer logic circuits and control said selector.

15. A circuit according to claim 10, further comprising a comparator to compare said circuit-output and cone-output of said at least one of said logic-cones.

16. A circuit according to claim 10, further comprising a Built-In-Self-Test (BIST) circuit.

17. A circuit according to claim 13 wherein the output of said selector is an input to first layer flip-flop.

18. A circuit according to claim 10 wherein said second layer is substantially the same as said first layer.

19. A circuit according to claim 13 wherein said selector comprises non-volatile programming.

20. An integrated circuit comprising:

a first layer of logic circuits, and

a second layer of logic circuits overlaying said first layer, wherein said first layer comprises a first combinatorial function, and said second layer comprises a second combinatorial function,

wherein said second combinatorial function overlays said first combinatorial function,

wherein said second combinatorial function is substantially the same as said first combinatorial function,

wherein said first layer comprises a multiplicity of flip-flops each flip-flop having connections to said second layer and wherein said connections are connected to the inputs to said second combinatorial function.

21. A circuit according to claim 20 wherein said connections are connected to the inputs to said first combinatorial function.

22. A circuit according to claim 20 wherein the output of said second combinatorial function is connected to said first layer.

23. A circuit according to claim 22 wherein said first layer comprises a selector to select between said output and a signal generated within said first layer.

24. A circuit according to claim 23, further comprising a controller which is adapted to perform testing of said first layer logic circuits and control said selector.

25. A circuit according to claim 23 wherein the output of said selector is an input to first layer said flip-flop.

26. An integrated circuit comprising:

a first layer of logic circuits, and

a second layer of logic circuits overlaying said first layer, wherein said first layer comprises a first combinatorial function, and said second layer comprises a second combinatorial function,

wherein said second combinatorial function overlays said first combinatorial function,

wherein said second combinatorial function is substantially the same as said first combinatorial function; and

a Built-In-Self-Test (BIST) circuit.