Low minimum power supply voltage level shifter

• US 8,493,124 B2
• Filed: 07/26/2010
• Issued: 07/23/2013
• Est. Priority Date: 07/26/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chern, Chan-Hong, Hsueh, Fu-Lung, Huang, Ming-Chieh, Lin, Chih-Chang
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US12/843,479
• Publication Number:
  US 20120019302A1
• Time in Patent Office: 1,093 Days
• Field of Search: 326 62- 63, 326 80- 81, 327/306, 327/333
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.

Claims

1. A level shifter, comprising:

a first NMOS transistor, a source of the first NMOS transistor arranged to be coupled to a low power supply voltage;

a second NMOS transistor;

a voltage input node arranged to receive an input signal and coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor, wherein the input signal has a voltage level up to a first power supply voltage;

a first PMOS transistor configured to selectively turn completely off, a source of the first PMOS transistor arranged to be coupled to a second power supply voltage that is higher than the first power supply voltage, a gate of the first PMOS transistor arranged to be coupled to a drain of the second NMOS transistor;

a voltage output node arranged to supply an output signal and to be coupled between the first PMOS transistor and the first NMOS transistor;

a second PMOS transistor, a source of the second PMOS transistor arranged to be coupled to the second power supply voltage and a drain of the second PMOS transistor arranged to be coupled to a drain of the second NMOS transistor; and

a third PMOS transistor arranged to be coupled to the first PMOS transistor, wherein a gate of the third PMOS transistor is coupled to the voltage input node,

wherein the first NMOS transistor is arranged to pull down the output signal to a low logic level when the input signal is a first logic level, and the second NMOS transistor is arranged to enable the first PMOS transistor to pull up the output signal to a high logic level at the second power supply voltage when the input signal is a second logic level.

2. The level shifter of claim 1, wherein a gate of the second NMOS transistor is arranged to be coupled to the first power supply voltage.

3. The level shifter of claim 1, wherein the third PMOS transistor is arranged to be coupled between the first PMOS transistor and the voltage output node to prevent the first PMOS transistor from pulling up the output signal to the high logic level when the input signal is at the first logic level.

4. The level shifter of claim 3, wherein a source of the third PMOS transistor is coupled to a drain of the first PMOS transistor.

5. The level shifter of claim 3, wherein a drain of the third PMOS transistor is coupled to a drain of the first NMOS transistor.

6. The level shifter of claim 3, wherein a source of the third PMOS transistor is arranged to be coupled to the second power supply voltage.

7. The level shifter of claim 3, wherein a drain of the second PMOS transistor is coupled to the gate of the first PMOS transistor.

8. The level shifter of claim 1, wherein a drain of the third PMOS transistor is coupled to a gate of the first PMOS transistor.

9. A method for a level shifter, comprising:

receiving an input signal having a voltage level up to a first power supply voltage, wherein the input signal is arranged to be coupled to a gate of a first NMOS transistor and a source of a second NMOS transistor;

pulling down an output signal to a low logic level by the first NMOS transistor when the input signal is a first logic level at the first power supply voltage;

preventing a first PMOS transistor from pulling up the output signal when the input signal is the first logic level by coupling a drain of a second PMOS transistor to a gate of the first PMOS transistor and a drain of the second NMOS transistor during an entire period of operation to selectively turn completely off the first PMOS transistor, and coupling a third PMOS transistor to the first PMOS transistor;

coupling the input signal to a gate of the third PMOS transistor; and

pulling up the output signal to a high logic level by the first PMOS transistor coupled to a second power supply voltage that is higher than the first power supply voltage when the input signal is a second logic level.

10. The method of claim 9, further comprising coupling a gate of the second NMOS transistor to the first power supply voltage.

11. The method of claim 9, further comprising preventing the first PMOS transistor from pulling up the output signal to a high logic level when the input signal is a first logic level by coupling the third PMOS transistor between the first PMOS transistor and the voltage output node.

12. The method of claim 11, further comprising coupling a source of the third PMOS transistor to a drain of the first PMOS transistor.

13. The method of claim 11, further comprising coupling a drain of the third PMOS transistor to a drain of the first NMOS transistor.

14. The method of claim 11, further comprising coupling a source of the third PMOS transistor to the second power supply voltage.

15. The method of claim 11, further comprising coupling a drain of the second PMOS transistor to the gate of the first PMOS transistor.

16. The method of claim 11, further comprising coupling a drain of the third PMOS transistor to the gate of the first PMOS transistor.

17. A level shifter, comprising:

a first NMOS transistor, a source of the first NMOS transistor arranged to be coupled to a low power supply voltage;

a second NMOS transistor, a gate of the second NMOS transistor arranged to be coupled to a first power supply voltage;

a voltage input node arranged to receive an input signal and coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor, wherein the input signal has a voltage level up to the first power supply voltage;

a first PMOS transistor configured to selectively turn completely off, a source of the first PMOS transistor arranged to be coupled to a second power supply voltage that is higher than the first power supply voltage;

a voltage output node arranged to supply an output signal and to be coupled between the first PMOS transistor and the first NMOS transistor;

a second PMOS transistor, a source of the second PMOS transistor arranged to be coupled to the second power supply voltage and a drain of the second PMOS transistor arranged to be coupled to a drain of the second NMOS transistor during an entire period of operation arranged to prevent the first PMOS transistor from pulling up the output signal to a high logic level when the input signal is a first logic level;

a third PMOS transistor coupled to the first PMOS transistor, the third PMOS transistor having a gate coupled to the voltage input signal,

wherein the first NMOS transistor is arranged to pull down the output signal to a low logic level when the input signal is the first logic level, and the second NMOS transistor is arranged to enable the first PMOS transistor to pull up the output signal to the high logic level at the second power supply voltage when the input signal is a second logic level.

18. The level shifter of claim 17, wherein a gate of the first PMOS transistor the drain of the second PMOS transistor.