RF switching system, module, and methods with improved high frequency performance

• US 8,493,128 B2
• Filed: 09/14/2011
• Issued: 07/23/2013
• Est. Priority Date: 04/30/2011
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Adamski, Jaroslaw
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US13/232,893
• Publication Number:
  US 20120274387A1
• Time in Patent Office: 678 Days
• Field of Search: 327/365, 327/376, 327/377, 327/427
• US Class Current: 327/365
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

Embodiments of radio frequency switching systems, modules, and methods with improved high frequency performance are described generally herein where the switching module may include a first switch module coupled in series to a second switch module, and a third switch module coupled between the first and the second module and ground. A controllable element of the second module may have a lower off capacitance than a controllable element of the first module. Other embodiments may be described and claimed.

Claims

1. A switch apparatus for communicating a signal received on a first port to a second port as a function of a first control signal, CS1, including:

a first switch module, SW1 coupled to the first port and an intermediate port, the SW1 including at least one controllable element, CE1, the CE1 controlled by the CS1 and having an off capacitance, OC1;

a second switch module, SW2 coupled to the intermediate port and the second port, the SW2 including at least one controllable element, CE2, the CE2 controllable by the CS1 and the CE2 having an off capacitance, OC2; and

a first shunt module, SH1 coupled to the intermediate port and ground, the SH1 including at least third controllable element, CE3, the SH1 controllable by a second control signal, CS2,

wherein OC1 is greater than OC2.

2. The switch apparatus of claim 1, wherein the SW1 elements total series off capacitance, TC1 is larger than the SW2 elements total series off capacitance, TC2.

3. The switch apparatus of claim 2, the SW1 including a plurality of serially coupled controllable elements, each controllable by the CS1 and having an off capacitance of about OC1 and the SW2 including a plurality of serially coupled controllable elements, each controllable by the CS1 and having an off capacitance of about OC2.

4. The switch apparatus of claim 3, wherein the SW1 has a total voltage handling capacity, VC1 and the SW2 has a total voltage handling capacity, VC2, and VC1 is smaller or about equal to VC2.

5. The switch apparatus of claim 3, wherein the SH1 has a total voltage handling capacity, VC3 and VC2 is about equal to VC3.

6. The switch apparatus of claim 2, wherein he CE1 has an effective resistance, R1, CE2 has an effective resistance, R2, and R1 is less than R2.

7. The switch apparatus of claim 2, wherein the SW1 elements are transistors, the SW2 elements are transistors, and the SH1 elements are transistors.

8. The switch apparatus of claim 2, wherein the SW1 elements are CMOS transistors, SW2 elements are CMOS transistors, and the SH1 elements are CMOS transistors.

9. The switch apparatus of claim 8, wherein the SW1 CMOS transistors gates and the SW2 CMOS transistors gates are coupled to the CS1 and the SH1 CMOS transistors gates are coupled to the CS2.

10. The switch apparatus of claim 2, further comprising a second shunt module, SH2 coupled to the first port and ground, the SH2 including at least a fourth controllable element, CE4, the SH2 controllable by the second control signal, CS2.

11. The switch apparatus of claim 10, further comprising one of an antenna node and a common node coupled to the first port and wherein the second port is coupled to the other of the antenna node and the common node.

12. The switch apparatus of claim 10, wherein the SW1 and the SW2 are radio frequency (RF) switches.

13. The switch apparatus of claim 10, wherein the SH2 has a total voltage handling capacity, VC4 and VC4 is about equal to VC3.

14. The switch apparatus of claim 13, wherein the SH2 elements are CMOS transistors.

15. The switch apparatus of claim 14, wherein the SH2 CMOS transistors gates are coupled to the CS2.

16. The switch apparatus of claim 2, wherein SW2 further includes another controllable element, CE5 coupled in series with the controllable element CE2, the CE5 controllable by the CS1 and the CE5 having an off capacitance, OC5 and wherein OC1 is greater than OC5.

17. A method of communicating a signal received on a first port to a second port as a function of a first control signal, CS1, including:

employing a first switch module, SW1 coupled to the first port and an intermediate port, the SW1 including at least a first controllable element, CE1, the CE1 controlled by the CS1 and having an off capacitance, OC1 to communicate the signal from the first port to the intermediate port when active;

employing a second switch module, SW2 coupled to the intermediate port and the second port, the SW2 including at least a second controllable element, CE2 , the CE2 controllable by the CS1 and the CE2 having an off capacitance, OC2 to communicate the signal from the intermediate port to the second port when active; and

employing a first shunt module, SH1 coupled to the intermediate port and ground, the SH1 including at least a third controllable element, CE3, the SH1 controllable by a second control signal, CS2 to communicate signals from the intermediate port to ground when active,

wherein OC1 is greater than OC2.

18. The method of claim 17, wherein the SW1 elements total series off-state capacitance, TC1 is larger than the SW2 elements total series off-state capacitance, TC2.

19. The method of claim 18, wherein the SW1 has a total series on resistance, R1, SW2 has a total series on resistance, R2 and R1 is less than R2.

20. The method of claim 18, wherein the SW1 and the SW2 are made active via the CS1 when the SH1 is made not active via the CS2 and the SW1 and SW2 are made inactive via the CS1 when the SH1 is made active via the CS2.