Semiconductor device and method of driving semiconductor device

• US 8,493,766 B2
• Filed: 02/02/2011
• Issued: 07/23/2013
• Est. Priority Date: 02/05/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kawae, Daisuke
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US13/019,334
• Publication Number:
  US 20110194327A1
• Time in Patent Office: 902 Days
• Field of Search: 365/72, 365/189.05
• US Class Current: 365/72
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 2211/4068 Voltage or leakage in refresh operations
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The number of wirings per unit memory cell is reduced by sharing a bit line by a writing transistor and a reading transistor. Data is written by turning on the writing transistor so that a potential of the bit line is supplied to a node where one of a source electrode and a drain electrode of the writing transistor and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined amount of charge is held in the node. Data is read by using a reading signal line connected to one of a source electrode and a drain electrode of the reading transistor so that a predetermined reading potential is supplied to the reading signal line, and then detecting a potential of the bit line.

Claims

1. A semiconductor device comprising:

a first memory cell and a second memory cell, each of the first memory cell and the second memory cell including a first transistor and a second transistor;

each of the first transistor and the second transistor in each of the first memory cell and the second memory cell comprising a gate, a source and a drain;

a first wiring electrically connected to one of the source and the drain of the first transistor of the first memory cell and one of the source and the drain of the first transistor of the second memory cell;

a second wiring electrically connected to the other of the source and the drain of the first transistor of the first memory cell and one of the source and the drain of the second transistor of the first memory cell;

a third wiring electrically connected to the other of the source and the drain of the first transistor of the second memory cell and one of the source and the drain of the second transistor of the second memory cell; and

a fourth wiring electrically connected to the gate of the second transistor of the first memory cell and the gate of the second transistor of the second memory cell,

wherein in each of the first memory cell and the second memory cell, the other of the source and the drain of the second transistor is electrically connected to the gate of the first transistor.

2. The semiconductor device according to claim 1, wherein the second transistor in each of the first memory cell and the second memory cell comprises an oxide semiconductor.

3. The semiconductor device according to claim 1, wherein an off-state current of the second transistor in each of the first memory cell and the second memory cell is lower than an off-state current of the first transistor.

4. The semiconductor device according to claim 1, wherein in each of the first memory cell and the second memory cell, a switching speed of the first transistor is higher than a switching speed of the second transistor.

5. A semiconductor device comprising:

a reading signal line;

a plurality of bit lines;

a word line;

a first driving circuit electrically connected to the reading signal line;

a second driving circuit electrically connected to the plurality of bit lines;

a third driving circuit electrically connected to the word line; and

a plurality of memory cells,

each of the plurality of memory cells comprising;

a first transistor and a second transistor;

each of the first transistor and the second transistor comprising a gate, a source and a drain;

wherein one of the source and the drain of the first transistor is electrically connected to the reading signal line,

wherein one of the source and the drain of the second transistor is electrically connected to the gate of the first transistor,

wherein the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor are electrically connected to one of the plurality of bit lines, and

wherein the gate of the second transistor is electrically connected to the word line.

6. The semiconductor device according to claim 5, wherein the second transistor comprises an oxide semiconductor.

7. The semiconductor device according to claim 5, wherein an off-state current of the second transistor is lower than an off-state current of the first transistor.

8. The semiconductor device according to claim 5, wherein a switching speed of the first transistor is higher than a switching speed of the second transistor.

9. A method for driving a semiconductor device comprising:

a memory cell including a first transistor and a second transistor;

each of the first transistor and the second transistor comprising a gate, a source and a drain;

a first wiring electrically connected to one of the source and the drain of the first transistor; and

a second wiring electrically connected to the other of the source and the drain of the first transistor and one of the source and the drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the gate of the first transistor,

the method for driving the semiconductor device comprising the steps of;

in a state where the first transistor is in an off state,

turning on the second transistor,

applying a high-level potential or a low-level potential which is supplied to the second wiring, to the gate of the first transistor; and

turning off the second transistor, whereby a potential of the gate of the first transistor is held.

10. The method for driving a semiconductor device according to claim 9, wherein a difference between the high-level potential and the low-level potential which are supplied to the second wiring is smaller than a threshold voltage of the first transistor.

11. A method for driving a semiconductor device comprising:

a memory cell including a first transistor and a second transistor;

each of the first transistor and the second transistor comprising a gate, a source and a drain;

a first wiring electrically connected to one of the source and the drain of the first transistor; and

a second wiring electrically connected to the other of the source and the drain of the first transistor and one of the source and the drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the gate of the first transistor,

the method for driving the semiconductor device comprising the steps of;

turning off the second transistor;

setting the second wiring at a second potential and then setting the first wiring at a first potential; and

detecting on or off of the first transistor.

12. The method for driving a semiconductor device according to claim 11, wherein the first potential is different from the second potential.