Interference mitigation using individual word line erasure operations

• US 8,493,781 B1
• Filed: 07/28/2011
• Issued: 07/23/2013
• Est. Priority Date: 08/12/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Meir, Avraham, Gurgi, Eyal, Dar, Ronen, Sommer, Naftali, Shalvi, Ofir
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Norman, James G
• Application Number:
  US13/192,504
• Time in Patent Office: 726 Days
• Field of Search: None
• US Class Current: 365/185.02
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells. The data is stored in a first group of the memory cells by programming a second group of the memory cells so as to cause the second group to generate interference in the first group, and individually erasing the first group while verifying that analog levels of the memory cells in the first group subject to the interference are within a predefined bound following erasure. After erasing the first group, the first group of the memory cells is programmed with the data.

Claims

1. A method for data storage, comprising:

accepting data for storage in a memory that includes multiple analog memory cells; and

storing the data in a first group of the memory cells, by;

programming a second group of the memory cells to a predefined high interference-generating threshold voltage wherein the predefined high interference-generating threshold voltage generates interference from the second group to the first group;

individually erasing the first group without erasing the second group, thereby subjecting the first group to interference from the second group;

verifying that analog levels of the memory cells in the first group subject to the interference are within a predefined bound following erasure; and

after erasing the first group, programming the first group of the memory cells with the data.

2. The method according to claim 1, wherein the memory cells are arranged in rows associated with respective word lines, wherein the first and second groups belong to first and second word lines, respectively, and wherein individually erasing the first group comprises individually erasing the first word line.

3. The method according to claim 1, wherein programming the second group comprises programming the memory cells in the second group to the predefined interference-generating value in response to a command to store the data in the first group.

4. The method according to claim 1, wherein programming the second group comprises initializing at least part of a memory block that comprises the first and second groups to the interference-generating value.

5. The method according to claim 4, wherein initializing at least the part of the memory block comprises accepting in the memory an initialization command from a controller, and initializing at least the part of the memory block in response to the initialization command.

6. The method according to claim 1, wherein programming the memory cells in the second group comprises setting one or more flags in the memory that indicate whether the second group is programmed to the predefined interference-generating value.

7. The method according to claim 1, wherein programming the second group comprises programming multiple word lines of the memory concurrently to the interference-generating value.

8. The method according to claim 7, wherein programming the multiple word lines comprises applying a single respective programming pulse to each of the multiple word lines.

9. The method according to claim 1, wherein programming the second group to the interference-generating value comprises retaining programming levels that were programmed in the second group in a previous block programming operation.

10. The method according to claim 1, wherein programming the second group comprises programming the memory cells of the second group with other data.

11. The method according to claim 1, wherein the first group is previously programmed with previous data, and wherein storing the data in the first group comprises reading and backing-up the previous data before erasing the first group, and, after erasing the first group, programming the first group with both the data and the backed-up previous data.

12. The method according to claim 1, wherein programming the first group comprises programming the memory cells in the first group to interim programming levels, subsequently programming at least one memory cell outside the first group, and subsequently re-programming the memory cells in the first group to final programming levels.

13. The method according to claim 12, wherein programming the first group to the interim programming levels comprises caching the data programmed to the first group in a buffer, and wherein re-programming the first group comprises re-programming the memory cells in the first group using the data cached in the buffer.

14. The method according to claim 1, wherein one of the first and second groups comprises the memory cells belonging to even-order word lines of the memory, and wherein the other of the first and second groups comprises the memory cells belonging to odd-order word lines of the memory.

15. The method according to claim 1, wherein the memory cells are arranged in rows associated with respective word lines, wherein one of the first and second groups comprises even-order memory cells in a given word line, and wherein the other of the first and second groups comprises odd-order memory cells in the given word line.

16. The method according to claim 1, wherein the memory is configurable to store the data in one of:

a first mode in which the first group is individually erased while subject to the interference from the second group; and

a second mode in which the first group is only erased during initialization of a memory block to which the first and second groups belong, and

wherein storing the data comprises accepting from a memory controller a command that indicates a selected one of the modes, and storing the data in the first group using the selected one of the modes.

17. Apparatus for data storage, comprising:

an interface, which is configured to accept data for storage in a memory that includes multiple analog memory cells; and

storage circuitry, which is configured to store the data in a first group of the memory cells by;

programming a second group of the memory cells to a predefined high interference-generating threshold voltage wherein the predefined high interference-generating threshold voltage generates interference from the second group to the first group;

individually erasing the first group without erasing the second group, thereby subjecting the first group to interference from the second group;

verifying that analog levels of the memory cells in the first group subject to the interference are within a predefined bound following erasure; and

after erasing the first group, programming the first group of the memory cells with the data.

18. The apparatus according to claim 17, wherein the memory cells are arranged in rows associated with respective word lines, wherein the first and second groups belong to first and second word lines, respectively, and wherein the storage circuitry is configured to individually erase the first group by individually erasing the first word line.

19. The apparatus according to claim 17, wherein the storage circuitry is configured to program the memory cells in the second group to the predefined interference-generating value in response to a command to store the data in the first group.

20. The apparatus according to claim 17, wherein the storage circuitry is configured to initialize at least part of a memory block that comprises the first and second groups to the interference-generating value.

21. The apparatus according to claim 20, wherein the storage circuitry is coupled to the memory, and is configured to accept an initialization command from a controller and to initialize at least the part of the memory block in response to the initialization command.

22. The apparatus according to claim 17, wherein the storage circuitry is configured to set one or more flags in the memory that indicate whether the second group is programmed to the predefined interference-generating value.

23. The apparatus according to claim 17, wherein the storage circuitry is configured to program multiple word lines of the memory concurrently to the interference-generating value.

24. The apparatus according to claim 23, wherein the storage circuitry is configured to program the multiple word lines by applying a single respective programming pulse to each of the multiple word lines.

25. The apparatus according to claim 17, wherein the storage circuitry is configured to program the second group to the interference-generating value by retaining programming levels that were programmed in the second group in a previous block programming operation.

26. The apparatus according to claim 17, wherein the storage circuitry is configured to program the memory cells of the second group with other data.

27. The apparatus according to claim 17, wherein the first group is previously programmed with previous data, and wherein the storage circuitry is configured to store the data in the first group by reading and backing-up the previous data before erasing the first group, and, after erasing the first group, programming the first group with both the data and the backed-up previous data.

28. The apparatus according to claim 17, wherein the storage circuitry is configured to program the memory cells in the first group to interim programming levels, to subsequently program at least one memory cell outside the first group, and to subsequently re-program the memory cells in the first group to final programming levels.

29. The apparatus according to claim 28, wherein the storage circuitry is configured to cache the data programmed to the first group in a buffer, and to re-program the memory cells in the first group using the data cached in the buffer.

30. The apparatus according to claim 17, wherein one of the first and second groups comprises the memory cells belonging to even-order word lines of the memory, and wherein the other of the first and second groups comprises the memory cells belonging to odd-order word lines of the memory.

31. The apparatus according to claim 17, wherein the memory cells are arranged in rows associated with respective word lines, wherein one of the first and second groups comprises even-order memory cells in a given word line, and wherein the other of the first and second groups comprises odd-order memory cells in the given word line.

32. The apparatus according to claim 17, wherein the storage circuitry is coupled to the memory, is configured to store the data in one of:

a first mode in which the first group is individually erased while subject to the interference from the second group; and

a second mode in which the first group is only erased during initialization of a memory block to which the first and second groups belong, and

is configured to accept from a memory controller a command that indicates a selected one of the modes, and to store the data in the first group using the selected one of the modes.

33. Apparatus for data storage, comprising:

a memory comprising multiple analog memory cells; and

storage circuitry, which is configured to store data in a first group of the memory cells by;

programming a second group of the memory cells to a predefined high interference-generating threshold voltage wherein the predefined high interference-generating threshold voltage generates interference from the second group to the first group;

individually erasing the first group without erasing the second group, thereby subjecting the first group to interference from the second group;

verifying that analog levels of the memory cells in the first group subject to the interference are within a predefined bound following erasure; and

after erasing the first group, programming the first group of the memory cells with the data.

34. A method for data storage, comprising:

accepting data for storage in a memory that includes multiple analog memory cells; and

storing the data in a first group of the memory cells, by;

programming a second group of the memory cells so as to cause the second group to generate interference in the first group;

individually erasing the first group while verifying that analog levels of the memory cells in the first group subject to the interference are within a predefined bound following erasure;

after erasing the first group, programming the first group of the memory cells with the data;

wherein programming the second group comprises predefining an interference-generating value, and programming the memory cells in the second group to the predefined interference-generating value; and

wherein programming the first group with the data comprises programming the first group using a first programming configuration having a first programming time, and wherein programming the second group to the interference-generating value comprises programming the second group using a second programming configuration having a second programming time, smaller than the first programming time.

35. Apparatus for data storage, comprising:

an interface, which is configured to accept data for storage in a memory that includes multiple analog memory cells; and

storage circuitry, which is configured to store the data in a first group of the memory cells by;

programming a second group of the memory cells so as to cause the second group to generate interference the first group;

individually erasing the first group while verifying that analog levels of the memory cells in the first group subject to the interference are within a predefined bound following erasure;

after erasing the first group, programming the first group of the memory cells with the data;

wherein the storage circuitry is configured to program the memory cells in the second group to a predefined interference-generating value; and

wherein the storage circuitry is configured to program the first group with the data using a first programming configuration having a first programming time, and to program the second group to the interference-generating value using a second programming configuration having a second programming time, smaller than the first programming time.

36. Apparatus for data storage, comprising:

a memory comprising multiple analog memory cells; and

storage circuitry, which is configured to store data in a first group of the memory cells by;

programming a second group of the memory cells so as to cause the second group to generate interference in the first group;

individually erasing the first group while verifying that analog levels of the memory cells in the first group subject to the interference are within a predefined bound following erasure;

after erasing the first group, programming the first group of the memory cells with the data;

wherein the storage circuitry is configured to program the memory cells in the second group to a predefined interference-generating value; and

wherein the storage circuitry is configured to program the first group with the data using a first programming configuration having a first programming time, and to program the second group to the interference-generating value using a second programming configuration having a second programming time, smaller than the first programming time.