Memory device readout using multiple sense times

• US 8,493,783 B2
• Filed: 10/30/2011
• Issued: 07/23/2013
• Est. Priority Date: 03/18/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Meir, Avraham, Baum, Barak, Sommer, Naftali
• Primary Examiner(s): Nuyen, Dang
• Application Number:
  US13/284,909
• Publication Number:
  US 20120320672A1
• Time in Patent Office: 632 Days
• Field of Search: 365/185.25, 365/185.09, 365/185.21, 365/185.03, 365/185.08, 365/185.18, 365/189.07, 365/222, 365/185.24, 365/185.01, 365/185.26, 365/185.28, 365/185.29
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A method for data storage includes storing data in a group of analog memory cells by writing respective storage values into the memory cells in the group. One or more of the memory cells in the group are read using a first readout operation that senses the memory cells with a first sense time. At least one of the memory cells in the group is read using a second readout operation that senses the memory cells with a second sense time, longer than the first sense time. The data stored in the group of memory cells is reconstructed based on readout results of the first and second readout operations.

Claims

1. A method for data storage, comprising:

storing data in a group of analog memory cells by writing respective storage values into the memory cells in the group;

reading one or more of the memory cells in the group using a first readout operation that senses the memory cells with a first sense time;

reading at least one of the memory cells in the group using a second readout operation that senses the memory cells with a second sense time, wherein the second sense time is longer than the first sense time; and

reconstructing the data stored in the group of memory cells based on readout results of the first and second readout operations;

wherein the memory cells in the group are coupled to respective bit lines, wherein reading using the first readout operation comprises charging the bit lines and measuring a discharge of the bit lines with the first sense time, and wherein reading using the second readout operation comprises measuring the discharge of the bit lines with the second sense time without re-charging the bit lines.

2. The method according to claim 1, wherein the memory cells in the group are associated with a single word line.

3. The method according to claim 1, wherein reading using the second readout operation comprises making an assessment of a success of the first readout operation, and performing the second readout operation only when the assessment indicates that the first readout operation failed.

4. The method according to claim 3, wherein making the assessment comprises estimating an occurrence frequency of a given data value in the memory cells in the group, and comparing the estimated occurrence frequency to an expected value.

5. The method according to claim 1, and comprising outputting at least part of the readout results of the first readout operation while simultaneously performing the second readout operation.

6. A method for data storage, comprising:

storing multiple parts of an Error Correction Code (ECC) code word in multiple respective groups of analog memory cells;

reading a first subset of the parts using a first readout configuration that reads the analog memory cells with a first sense time;

reading a second subset of the parts, different from the first subset, using a second readout configuration that reads the analog memory cells with a second sense time, wherein the second sense time is longer than the first sense time; and

decoding the ECC code word using the read first and second subsets;

wherein each of the analog memory cells holds at least first and second bits, and wherein storing the parts comprises storing the parts that are to be read using the first readout configuration in the first bits, and storing the parts that are to be read using the second readout configuration in the second bits.

7. The method according to claim 6, wherein storing the multiple parts comprises storing the parts in respective different memory devices, and wherein reading the first and second subsets comprises reading the multiple parts from the respective memory devices simultaneously.

8. The method according to claim 7, and comprising reading the multiple parts of an additional ECC code word from the multiple respective memory devices, such that the first and second subsets used in reading the parts of the additional code word are different from the first and second subsets used for reading the parts of the code word.

9. Apparatus for data storage, comprising:

multiple analog memory cells; and

circuitry, which is configured to store data in a group of the analog memory cells by writing respective storage values into the memory cells in the group, to read one or more of the memory cells in the group using a first readout operation that senses the memory cells with a first sense time, to read at least one of the memory cells in the group using a second readout operation that senses the memory cells with a second sense time, wherein the second sense time is longer than the first sense time, and to reconstruct the data stored in the group of memory cells based on readout results of the first and second readout operations;

wherein the memory cells in the group are coupled to respective bit lines, and wherein the circuitry is configured to read using the first readout operation by charging the bit lines and measuring a discharge of the bit lines with the first sense time, and to read using the second readout operation by measuring the discharge of the bit lines with the second sense time without re-charging the bit lines.

10. The apparatus according to claim 9, wherein the memory cells in the group are associated with a single word line.

11. The apparatus according to claim 9, wherein the circuitry is configured to make an assessment of a success of the first readout operation, and to perform the second readout operation only when the assessment indicates that the first readout operation failed.

12. The apparatus according to claim 11, wherein the circuitry is configured to make the assessment by estimating an occurrence frequency of a given data value in the memory cells in the group and comparing the estimated occurrence frequency to an expected value.

13. The apparatus according to claim 9, wherein the circuitry is configured to output at least part of the readout results of the first readout operation while simultaneously performing the second readout operation.

14. Apparatus for data storage, comprising:

multiple analog memory cells; and

circuitry, which is configured to store multiple parts of an Error Correction Code (ECC) code word in multiple respective groups of analog memory cells, to read a first subset of the parts using a first readout configuration that reads the analog memory cells with a first sense time, to read a second subset of the parts, different from the first subset, using a second readout configuration that reads the analog memory cells with a second sense time, wherein the second sense time is longer than the first sense time, and to decode the ECC code word using the read first and second subsets;

wherein each of the analog memory cells holds at least first and second bits, and wherein the circuitry is configured to store the parts that are to be read using the first readout configuration in the first bits, and to store the parts that are to be read using the second readout configuration in the second bits.

15. The apparatus according to claim 14, wherein the circuitry is configured to store the multiple parts in respective different memory devices, and to read the multiple parts from the respective memory devices simultaneously.

16. The apparatus according to claim 15, wherein the circuitry is configured to read the multiple parts of an additional ECC code word from the multiple respective memory devices, such that the first and second subsets used in reading the parts of the additional code word are different from the first and second subsets used for reading the parts of the code word.