Sense-amplifier circuit of memory and calibrating method thereof

• US 8,493,806 B1
• Filed: 01/03/2012
• Issued: 07/23/2013
• Est. Priority Date: 01/03/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Shi-Wen
• Primary Examiner(s): Lam, David
• Application Number:
  US13/342,253
• Publication Number:
  US 20130170309A1
• Time in Patent Office: 567 Days
• Field of Search: 365/207, 365/205, 365/189.09, 365/189.11
• US Class Current: 365/207
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A sense-amplifier circuit of a memory, which includes a sense-amplifier unit, a first switch unit and a second switch unit. The sense-amplifier unit is constituted by a plurality of transistor switches and having a first, a second, a third and a fourth connection terminal. The first switch unit is configured to be parallel coupled between the first and second connection terminals of the sense-amplifier unit. The second switch unit is configured to be parallel coupled between the third and fourth connection terminals of the sense-amplifier unit. The first and second switch units each are constituted by a plurality of transistor switches coupled in parallel and are configured to control each of the parallel-coupled transistor switches on or off in the first and second switch units so as to calibrate a sensing range of the sense-amplifier unit. A calibrating method for a sense-amplifier circuit of a memory is also provided.

Claims

1. A sense-amplifier circuit of a memory, comprising:

a sense-amplifier unit constituted by a plurality of transistor switches and having a first connection terminal, a second connection terminal, a third connection terminal and a fourth connection terminal;

a first switch unit configured to be parallel coupled between the first and second connection terminals of the sense-amplifier unit; and

a second switch unit configured to be parallel coupled between the third and fourth connection terminals of the sense-amplifier unit;

wherein the first and second switch units each are constituted by a plurality of transistor switches coupled in parallel and are configured to control each of the parallel-coupled transistor switches on or off in the first and second switch units so as to calibrate a sensing range of the sense-amplifier unit.

2. The sense-amplifier circuit according to claim 1, further comprising:

a control unit configured to electrically couple to the first and third connection terminals of the sense-amplifier unit thereby forming a first feedback path and a second feedback path, respectively, the control unit having a plurality of output terminals configured to electrically couple to the parallel-coupled transistor switches gate terminals of which in the first and second switch units with one to one correspondence;

wherein the control unit is configured to receive two feedback voltages from the first and second feedback paths and accordingly generate control signals for turning on the parallel-coupled transistor switches in the first and second switch units.

3. The sense-amplifier circuit according to claim 2, wherein the sense-amplifier unit further comprises:

a first switch having a drain terminal electrically coupled to the first connection terminal and a gate terminal electrically coupled to the third connection terminal;

a second switch having a drain terminal electrically coupled to the third connection terminal, a gate terminal electrically coupled to the first connection terminal and a source terminal electrically coupled to the source terminal of the first switch;

a third switch having a drain terminal electrically coupled to the first connection terminal, a gate terminal electrically coupled to the third connection terminal and a source terminal electrically coupled to the second connection terminal;

a fourth switch having a drain terminal electrically coupled to the third connection terminal, a gate terminal electrically coupled to the first connection terminal and a source terminal electrically coupled to the fourth connection terminal;

a fifth switch having a drain terminal electrically coupled to both the source terminals of the third and fourth switches, a gate terminal configured to receive an enable signal and a source terminal electrically coupled to ground;

a sixth switch having a source terminal configured to receive a bit-line signal, a gate terminal configured to receive the enable signal and a drain terminal electrically coupled to the third connection terminal;

a seventh switch having a drain terminal electrically coupled to the source terminal of the sixth switch, a gate terminal configured to receive a complementary bit-line signal and a source terminal electrically coupled to the third connection terminal;

an eighth switch having a source terminal configured to receive a complementary bit-line signal, a gate terminal configured to receive the enable signal and a drain terminal electrically coupled to the first connection terminal; and

a ninth switch having a drain terminal electrically coupled to the source terminal of the eighth switch, a gate terminal configured to receive the complementary enable signal and a source terminal electrically coupled to the first connection terminal;

wherein the first and second connection terminals are further configured to be electrically coupled to a first and a second input terminals of the control unit so as to form the first and second feedback paths, respectively.

4. The sense-amplifier circuit according to claim 1, wherein the parallel-coupled transistor switches in the first and second switch units each have a same channel width to length ratio.

5. The sense-amplifier circuit according to claim 1, wherein the parallel-coupled transistor switches in the first and second switch units each have a different channel width to length ratio.

6. The sense-amplifier circuit according to claim 1, wherein the first and second switch units each have a same number of parallel-coupled transistor switches.

7. The sense-amplifier circuit according to claim 1, wherein in the first switch unit the innermost transistor switch has a greatest width to length ratio relative to the rest transistor switches, and in the second switch unit the innermost transistor switch has a greatest width to length ratio relative to the rest transistor switches.

8. The sense-amplifier circuit according to claim 7, wherein the innermost transistor switch in the first switch unit has a channel width to length ratio equal to that of the innermost transistor switch in the second switch unit.

9. A calibrating method for a sense-amplifier circuit, comprising steps of:

providing the sense-amplifier circuit, comprising;

a sense-amplifier unit constituted by a plurality of transistor switches and having a first connection terminal, a second connection terminal, a third connection terminal and a fourth connection terminal;

a first switch unit configured to be parallel coupled between the first and second connection terminals of the sense-amplifier unit;

a second switch unit configured to be parallel coupled between the third and fourth connection terminals of the sense-amplifier unit; and

a control unit configured to electrically couple to the first and third connection terminals of the sense-amplifier unit thereby forming a first feedback path and a second feedback path, respectively, the control unit having a plurality of output terminals configured to electrically couple to the parallel-coupled transistor switches gate terminals of which in the first and second switch units with one to one correspondence;

simultaneously supplying a same voltage signal to the first and third connection terminals of the sense-amplifier unit;

detecting a voltage level at each of the first and third connection terminals of the sense-amplifier unit in a next clock sequence and determining whether or not the first and third connection terminals have a same voltage level; and

outputting at least a control signal to the parallel-coupled transistor switches gate terminals of which from the control unit if the first connection terminal has a different voltage level from the third connection terminal, wherein the control signal selectively turns on at least a parallel-coupled transistor switch in the first or second switch units so as to calibrate a sensing range of the sense-amplifier unit.

10. The calibrating method for a sense-amplifier circuit of a memory according to claim 9, wherein the control signal turns on at least a parallel-coupled transistor switch in the first switch unit if the first connection terminal has a higher voltage level than the third connection terminal has.

11. The calibrating method for a sense-amplifier circuit of a memory according to claim 9, wherein the control signal turns on at least a parallel-coupled transistor switch in the second switch unit if the third connection terminal has a higher voltage level than the first connection terminal has.