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Data flow control in multiple independent port

  • US 8,493,808 B2
  • Filed: 03/13/2012
  • Issued: 07/23/2013
  • Est. Priority Date: 02/22/2007
  • Status: Expired due to Fees
First Claim
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1. A memory device for use in a serial interconnection configuration comprising a plurality of memory devices connected in-series, each of the memory devices being addressable based on device identification (ID), the memory device comprising:

  • a receiver configured to receive an input port enable signal, a serial input signal and an output port enable signal, the receiver comprising;

    a first input buffer configured to receive the input port enable signal and to provide an internal input enable signal;

    a second input buffer configured to receive the serial input signal and to provide an internal serial input signal; and

    a third input buffer configured to receive the output port enable signal and to provide an internal output enable signal; and

    an output provider configured to output a serial output signal, an echo of the input port enable signal and an echo of the output port enable signal, the output provider comprises;

    logic circuitry configured toreceive the internal serial input signal and the internal input enable signal, andprovide an input signal to a first flip-flop; and

    a selector configured toreceive an output signal of the first flip-flop,receive an internal serial output signal,receive an ID match signal, andselect the output signal from the first flip-flop when the ID match signal is de-asserted or select the internal serial output signal when the ID match signal is asserted.

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