Data flow control in multiple independent port
First Claim
1. A memory device for use in a serial interconnection configuration comprising a plurality of memory devices connected in-series, each of the memory devices being addressable based on device identification (ID), the memory device comprising:
- a receiver configured to receive an input port enable signal, a serial input signal and an output port enable signal, the receiver comprising;
a first input buffer configured to receive the input port enable signal and to provide an internal input enable signal;
a second input buffer configured to receive the serial input signal and to provide an internal serial input signal; and
a third input buffer configured to receive the output port enable signal and to provide an internal output enable signal; and
an output provider configured to output a serial output signal, an echo of the input port enable signal and an echo of the output port enable signal, the output provider comprises;
logic circuitry configured toreceive the internal serial input signal and the internal input enable signal, andprovide an input signal to a first flip-flop; and
a selector configured toreceive an output signal of the first flip-flop,receive an internal serial output signal,receive an ID match signal, andselect the output signal from the first flip-flop when the ID match signal is de-asserted or select the internal serial output signal when the ID match signal is asserted.
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Accused Products
Abstract
A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller.
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Citations
15 Claims
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1. A memory device for use in a serial interconnection configuration comprising a plurality of memory devices connected in-series, each of the memory devices being addressable based on device identification (ID), the memory device comprising:
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a receiver configured to receive an input port enable signal, a serial input signal and an output port enable signal, the receiver comprising; a first input buffer configured to receive the input port enable signal and to provide an internal input enable signal; a second input buffer configured to receive the serial input signal and to provide an internal serial input signal; and a third input buffer configured to receive the output port enable signal and to provide an internal output enable signal; and an output provider configured to output a serial output signal, an echo of the input port enable signal and an echo of the output port enable signal, the output provider comprises; logic circuitry configured to receive the internal serial input signal and the internal input enable signal, and provide an input signal to a first flip-flop; and a selector configured to receive an output signal of the first flip-flop, receive an internal serial output signal, receive an ID match signal, and select the output signal from the first flip-flop when the ID match signal is de-asserted or select the internal serial output signal when the ID match signal is asserted. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification