Single instruction processing of network packets
First Claim
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1. A method comprising:
- providing a single instruction/multiple data (SIMD) program to process a first vector of data wherein each element of the first vector corresponds to a different received packet;
the program comprising instructions which, when executed, cause SIMD processing comprising;
accessing a second vector, wherein each element of the second vector identifies occupancy of a corresponding element in the first vector;
accessing a third vector, wherein each element of the third vector comprises flow state data for a flow of an associated packet in the first vector; and
modifying elements in the third vector.
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Abstract
Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet.
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Citations
30 Claims
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1. A method comprising:
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providing a single instruction/multiple data (SIMD) program to process a first vector of data wherein each element of the first vector corresponds to a different received packet; the program comprising instructions which, when executed, cause SIMD processing comprising; accessing a second vector, wherein each element of the second vector identifies occupancy of a corresponding element in the first vector; accessing a third vector, wherein each element of the third vector comprises flow state data for a flow of an associated packet in the first vector; and modifying elements in the third vector. - View Dependent Claims (2, 3, 4)
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5. A network interface controller, comprising:
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an interface to a PHY; a Direct Memory Access (DMA) engine to transfer data from the network interface controller to memory; circuitry to arrange data of packets into a vector, wherein each element of the vector corresponds to a different packet, for single instruction/multiple data (SIMD) processing of the vector; wherein the circuitry to arrange data of the packets into a vector comprises circuitry to arrange data of the packets into a vector where each element of the vector corresponds to a same strict subset of packet header fields. - View Dependent Claims (6, 7)
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8. A method, comprising:
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determining if a network interface controller has a capability to transfer packet header data into vectors of packet header data wherein each vector element is associated with a different packet; and configuring the network interface controller to transfer packet header data into vectors of packet header data, the configuring identifying the packet header data to transfer; and processing a vector of data within each of set of packets of a packet vector, wherein each element of the packet vector corresponds to a different packet. - View Dependent Claims (9)
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10. A computer program disposed on a non-transitory computer readable medium comprising instructions for causing circuitry to:
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access a vector of network packet data, individual vector elements comprising a strict subset of fields of a network packet header, respective vector elements corresponding to different respective network packets; and cause single instruction, parallel processing of the respective vector elements corresponding to the different respective network packets. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 20, 21)
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- 18. The program of 10, wherein the single instruction, parallel processing of the respective vector elements comprises updating of flow state data associated with the respective network packets.
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22. A system comprising:
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at least one processor capable of single instruction, parallel processing of vector elements; logic, when in operation, to; access a vector of network packet data, individual vector elements comprising a strict subset of fields of a network packet header, respective vector elements corresponding to different respective network packets; and cause single instruction, parallel processing by the at least one processor of the respective vector elements corresponding to the different respective network packets. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30)
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Specification