Single instruction processing of network packets

• US 8,493,979 B2
• Filed: 12/30/2008
• Issued: 07/23/2013
• Est. Priority Date: 12/30/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Veal, Bryan E., Schluessler, Travis T.
• Primary Examiner(s): PHUNKULH, BOB A
• Application Number:
  US12/317,844
• Publication Number:
  US 20100165991A1
• Time in Patent Office: 1,666 Days
• Field of Search: None
• US Class Current: 370/392
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element

Abstract

Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet.

Claims

1. A method comprising:

providing a single instruction/multiple data (SIMD) program to process a first vector of data wherein each element of the first vector corresponds to a different received packet;

the program comprising instructions which, when executed, cause SIMD processing comprising;

accessing a second vector, wherein each element of the second vector identifies occupancy of a corresponding element in the first vector;

accessing a third vector, wherein each element of the third vector comprises flow state data for a flow of an associated packet in the first vector; and

modifying elements in the third vector.

2. The method of claim 1,

wherein each element of the vector corresponds to a same strict subset of packet header fields.

3. The method of claim 1, further comprising instructions which, when executed, cause SIMD processing comprising:

determining a packet should not be processed by the SIMD instructions.

4. The method of claim 1, wherein the SIMD program comprises at least a portion of the program to perform at least one of the following:

determine protocols of the packets;

validate the packets;

compute header values for the packets; and

determine an execution unit to handle the packets.

5. A network interface controller, comprising:

an interface to a PHY;

a Direct Memory Access (DMA) engine to transfer data from the network interface controller to memory;

circuitry to arrange data of packets into a vector, wherein each element of the vector corresponds to a different packet, for single instruction/multiple data (SIMD) processing of the vector;

wherein the circuitry to arrange data of the packets into a vector comprises circuitry to arrange data of the packets into a vector where each element of the vector corresponds to a same strict subset of packet header fields.

6. The network interface controller of claim 5, further comprising circuitry to assign packets to the vector such that the vector includes elements corresponding to multiple packets belonging to the same flow.

7. The network interface controller of claim 5, further comprising circuitry to assign packets to the vector such that the vector does not include elements corresponding to multiple packets belonging to the same flow.

8. A method, comprising:

determining if a network interface controller has a capability to transfer packet header data into vectors of packet header data wherein each vector element is associated with a different packet; and

configuring the network interface controller to transfer packet header data into vectors of packet header data, the configuring identifying the packet header data to transfer; and

processing a vector of data within each of set of packets of a packet vector, wherein each element of the packet vector corresponds to a different packet.

9. The method of claim 8, further comprising:

determining whether a packet of the packet vector should thereafter be processed by instructions comprised entirely of MIMD (multiple instruction/multiple data) instructions.

10. A computer program disposed on a non-transitory computer readable medium comprising instructions for causing circuitry to:

access a vector of network packet data, individual vector elements comprising a strict subset of fields of a network packet header, respective vector elements corresponding to different respective network packets; and

cause single instruction, parallel processing of the respective vector elements corresponding to the different respective network packets.

11. The program of claim 10, wherein the single instruction, parallel processing of the respective vector elements comprises a forwarding lookup.

12. The program of claim 10, wherein the single instruction, parallel processing of the respective vector elements comprises a hash based on data included in the strict subset of fields of the respective network packet header.

13. The program of claim 10, wherein the network packet header comprises a Transmission Control Protocol (TCP) segment header.

14. The program of claim 10, wherein the network packet header comprises an Internet Protocol (IP) datagram header.

15. The program of claim 10, wherein strict subset of fields comprise at least one field from a Transmission Control Protocol (TCP) segment header and at least one field from an Internet Protocol (IP) datagram header.

16. The program of claim 10, wherein the vector of network packet data comprises data arranged by circuitry of a network interface controller, the network interface controller comprising, at least, an interface to a PHY.

17. The program of claim 10, wherein the vector of network packet data comprises data previously transferred to a memory by a Direct Memory Access (DMA) from a network interface controller.

20. The program of claim 10,

wherein the single instruction, parallel processing comprises SIMD(Single Instruction, Multiple Data) processing.

21. The program of claim 10,

further comprising extracting the strict subset of fields from a packet.

18. The program of 10, wherein the single instruction, parallel processing of the respective vector elements comprises updating of flow state data associated with the respective network packets.

19. The program of claim 18, wherein the flow state data comprises a vector of flow state data, where respective elements of the vector of flow state data correspond to the respective network packets of the vector of network packet data.

22. A system comprising:

at least one processor capable of single instruction, parallel processing of vector elements;

logic, when in operation, to;

access a vector of network packet data, individual vector elements comprising a strict subset of fields of a network packet header, respective vector elements corresponding to different respective network packets; and

cause single instruction, parallel processing by the at least one processor of the respective vector elements corresponding to the different respective network packets.

23. The system of claim 22, wherein the single instruction, parallel processing of the respective vector elements comprises a forwarding lookup.

24. The system of claim 22, wherein the single instruction, parallel processing of the respective vector elements comprises a hash based on data included in the strict subset of fields.

25. The system of claim 22, wherein the at least one network packet header comprises a Transmission Control Protocol (TCP) segment header.

26. The system of claim 22, wherein the at least one network packet header comprises an Internet Protocol (IP) datagram header.

27. The system of claim 22, wherein strict subset of fields comprise at least one field from a Transmission Control Protocol (TCP) segment header and at least one field from an Internet Protocol (IP) datagram header.

28. The system of claim 22, further comprising a network interface controller comprising:

an interface to a PHY;

a Direct Memory Access (DMA) engine; and

circuitry to cause DMA of network packet data into the array vector of network packet data.

29. The system of claim 22, wherein the single instruction, parallel processing of the respective vector elements comprises updating of flow state data associated with the respective network packets.

30. The system of claim 29, wherein the flow state data comprises a vector of flow state data, where respective elements of the vector of flow state data correspond to the respective network packets of the vector of network packet data.