Network clock synchronization timestamp

• US 8,494,009 B2
• Filed: 04/16/2007
• Issued: 07/23/2013
• Est. Priority Date: 09/25/2006
• Status: Active Grant

• Current Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Inventors: Fourcand, Serge Francois
• Primary Examiner(s): HOANG, THAI D
• Application Number:
  US11/735,592
• Publication Number:
  US 20080075120A1
• Time in Patent Office: 2,290 Days
• Field of Search: 370503-520, 375229-236, 375362-368
• US Class Current: 370/509
• CPC Class Codes: H04J 3/0602 Systems characterised by the synchronising information used
• CPC Class Codes: H04J 3/065 using timestamps
• CPC Class Codes: H04J 3/0667 Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays arrangements for monitoring round trip delays in packet switching networks H04L43/0864

Abstract

A network component comprising at least one processor configured to promote transmission of a frame from a first node to a second node, the frame comprising a first clock synchronization data, and a first frame count, wherein the first clock synchronization data and the first frame count are used to synchronize a first clock in the first node and a second clock in the second node. Also disclosed is a method comprising processing a frame comprising an Ethernet control symbol that delineates the beginning of the frame, a first clock synchronization data, a first frame count, and a second clock synchronization data. Included is an Ethernet node comprising at least one processor configured to synchronize a clock using a clock synchronization data comprising a first timestamp, a first frame count, a second timestamp, and a second frame count.

Claims

1. A network component comprising:

at least one processor coupled to a memory and configured to promote transmission of a frame from a first node to a second node, the frame comprising an Open System Interconnection (OSI) layer two header and a payload, wherein the OSI layer two header comprises;

a clock synchronization data; and

a frame count,

wherein the clock synchronization data and the frame count are used to synchronize a second clock in the second node with a first clock in the first node,

wherein the clock synchronization data is about four octets long and comprises a timestamp that is about three octets long and a control field that is about one octet long, and

wherein the frame count is about three octets long and comprises a timestamp that is about two octets long and a control field that is about one octet long.

2. The component of claim 1, wherein the frame is one of a plurality of frames with similar data structures, and wherein the frames are transmitted on intervals of about 125 microseconds.

3. The component of claim 1, wherein the clock synchronization data has a resolution of about 0.01 nanoseconds, wherein the clock synchronization data has a range of no more than about 168 microseconds, and wherein the clock synchronization data has a period of about 125 microseconds.

4. The component of claim 1, wherein a frame comprises:

an Ethernet control symbol that delineates the beginning of the frame;

a first clock synchronization data;

a frame count that comprises a timestamp and a control field; and

a second clock synchronization data.

5. The component of claim 1, wherein the frame count has a resolution of about 125 microseconds, wherein the frame count has a range of no more than about 8 seconds, and wherein the frame count has a period of about 125 microseconds.

6. The component of claim 1, wherein the OSI layer two header further comprises a start of frame delimiter, and wherein the clock synchronization data is positioned between the start of frame delimiter and the payload.

7. A method implemented by at least one processor coupled to a memory, the method comprising:

processing a frame comprising an Open System Interconnection (OSI) layer two header and a payload, wherein the OSI layer two header comprises;

an Ethernet control symbol that delineates the beginning of the frame;

a first clock synchronization data;

a frame count; and

a second clock synchronization data,

wherein the first dock synchronization data is about four octets long and comprises a timestamp that is about three octets long and a control field that is about one octet long, and

wherein the frame count is about three octets long and comprises a timestamp that is about two octets long and a control field that is about one octet long.

8. The method of claim 7, wherein the first clock synchronization data is associated with a transmission time of the frame and used to synchronize clock frequency.

9. The method of claim 8, wherein the second clock synchronization data is a transport delay between a first node and a second node and used to synchronize clock phase.

10. The method of claim 8, wherein the second clock synchronization data is a downstream node delay and used to synchronize clock phase.

11. The method of claim 7, wherein the frame interrupts an Ethernet packet.

12. The method of claim 11, wherein the Ethernet packet continues after the frame ends.

13. The method of claim 11, wherein the Ethernet packet and the frame are transmitted on the same interface.

14. The method of claim 7, wherein the OSI layer two header further comprises a timeslot map, and wherein the first clock synchronization data is positioned between the Ethernet control symbol and the timeslot map.

15. A node comprising:

at least one processor coupled to a memory and configured to synchronize a clock using a clock synchronization data generated by an Open System Interconnection (OSI) layer two component in another node, wherein the clock synchronization data comprises;

a first timestamp;

a first frame count;

a second timestamp; and

a second frame count,

wherein the clock synchronization data is about four octets long and comprises a timestamp that is about three octets long and a control field that is about one octet long, and

wherein the frame count is about three octets long and comprises a timestamp that is about two octets long and a control field that is about one octet long.

16. The node of claim 15, wherein the clock synchronization data is received about every 125 microseconds, and wherein the clock synchronization data is part of an Ethernet frame comprising an Ethernet control symbol that delineates the beginning of the frame, a frame count, and a second clock synchronization data.

17. The node of claim 15, wherein the first timestamp is associated with a transmission time of a frame comprising the clock synchronization data, wherein the first frame count differentiates the frame from a plurality of other similar frames, and wherein the second clock synchronization data is a transport delay between a first node and a second node or a downstream node delay.

18. The node of claim 15, wherein the frame is an OSI layer two frame comprising an OSI layer two header and a payload, wherein the header comprises a start of frame delimiter, the first timestamp, the first frame count, the second timestamp, and the second frame count, in the order listed.

19. The node of claim 18, wherein the start of frame delimiter is an

Ethernet control symbol.

20. The node of claim 18, wherein the OSI layer two header further comprises a timeslot map following the second frame count.