Method and system for 60 GHz wireless clock distribution

• US 8,494,030 B2
• Filed: 08/15/2008
• Issued: 07/23/2013
• Est. Priority Date: 06/19/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza
• Primary Examiner(s): Washburn, Daniel
• Assistant Examiner(s): HUGHES, EBONI N
• Application Number:
  US12/192,653
• Publication Number:
  US 20090316846A1
• Time in Patent Office: 1,803 Days
• Field of Search: 375/220, 375/260, 375/267, 455/8, 455/15, 455/25, 455/67.15, 455/426.1
• US Class Current: 375/219
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04W 56/00 Synchronisation arrangements

Abstract

Aspects of a method and system for 60 GHz wireless clock distribution may include configuring a microwave communication link established between a first chip and a second chip via a wireline communication bus. The configuration may comprise adjusting beamforming parameters of a first antenna array communicatively coupled to the first chip, and of a second antenna array communicatively coupled to the second chip. The first chip and the second chip may communicate a clock signal via the microwave communication link. The microwave communication link may be routed via one or more relay chips, when the first chip and the second chip cannot directly communicate. Control data may be transferred between the first chip, the second chip, and/or the one or more relay chips, which may comprise one or more antennas. The relay chips may be dedicated relay ICs or multi-purpose transmitter/receivers.

Claims

1. A method, the method comprising:

in a first chip;

configuring a first wireless link established between said first chip and a second chip by communicating messages over a wireline communication bus that directly connects said first chip and said second chip;

configuring a second wireless link established between said first chip and a third chip by communicating messages over said wireline communication bus that directly connects said first chip and said third chip; and

relaying a clock signal from said third chip to said second chip via said first wireless link and said second wireless link.

2. The method according to claim 1, comprising performing said relaying when said third chip and said second chip cannot directly communicate.

3. The method according to claim 2, wherein said messages communicated over said wireline communication bus that directly connects said first chip and said second chip, and said messages communicated over said wireline communication bus that directly connects said first chip and said third chip comprise control data.

4. The method according to claim 2, wherein said first chip comprises one or more antennas.

5. The method according to claim 2, wherein said first chip is a dedicated relay IC.

6. The method according to claim 2, wherein said first chip is a multi-purpose transmitter/receiver.

7. The method according to claim 1, wherein said first wireless link and said second wireless link operate in the 60 GHz frequency band.

8. The method according to claim 1, wherein configuring said first wireless link comprises adjusting beamforming parameters of a first antenna array communicatively coupled to said first chip, and of a second antenna array communicatively coupled to said second chip.

9. The method according to claim 8, wherein said first antenna array is on an integrated circuit package, or on an integrated circuit of said first chip.

10. The method according to claim 8, wherein said second antenna array is on an integrated circuit package, or on an integrated circuit of said second chip.

11. The method according to claim 8, wherein said first antenna array and said second antenna array each comprise a plurality of antennas.

12. The method according to claim 8, comprising adjusting said beamforming parameters to optimize a wireless clock distribution performance metric.

13. A system, the system comprising:

one or more circuits for use in a first chip, said first chip being directly connected to a second chip via a wireline communication bus, said first chip being directly connected to a third chip via a wireline communication bus, and said first chip being operable to;

configure a first wireless link established between said first chip and said second chip by communicating messages over said wireline communication bus that directly connects said first chip and said second chip;

configure a second wireless link established between said first chip and said third chip by communicating messages over said wireline communication bus that directly connects said first chip and said third chip; and

relay a clock signal from said third chip to said second chip via said first wireless link and said second wireless link.

14. The system according to claim 13, wherein said one or more circuits perform said relaying when said third chip and said second chip cannot directly communicate.

15. The system according to claim 14, wherein said messages communicated over said wireline communication bus that directly connects said first chip and

said second chip, and said messages communicated over said wireline communication bus that directly connects said first chip and said third chip comprise control data.

16. The system according to claim 14, wherein said first chip comprises one or more antennas.

17. The system according to claim 14, wherein said first chip is a dedicated relay chip.

18. The system according to claim 14, wherein said relay chip is a multi-purpose transmitter/receiver.

19. The system according to claim 13, wherein said first wireless link and said second wireless link operate in the 60 GHz frequency band.

20. The system according to claim 13, wherein configuring said first wireless link comprises adjustment of beamforming parameters of a first antenna array communicatively coupled to said first chip, and of a second antenna array communicatively coupled to said second chip.

21. The system according to claim 20, wherein said first antenna array is on an integrated circuit package, or on an integrated circuit of said first chip.

22. The system according to claim 20, wherein said second antenna array is on an integrated circuit package, or on an integrated circuit of said second chip.

23. The system according to claim 20, wherein said one or more chips adjust said beamforming parameters to optimize a wireless clock distribution performance metric.

24. A relay device having a wired connection to a plurality of wireless devices, the relay device comprising:

a processor that operates to configure a plurality of wireless links by communicating messages over the wired connection, each of the plurality of wireless links being established between the relay device and a wireless device in the plurality of wireless devices; and

a circuit that operates to relay a clock signal from a first wireless device of the plurality of wireless devices to a second wireless device of the plurality of wireless devices via at least two of the plurality of wireless links.