Intra-block memory wear leveling
First Claim
1. A method for intra-block wear leveling within solid-state memory subjected to wear, and having a plurality of memory cells arranged in blocks, the method comprising the step of:
- writing to at least certain ones of the plurality of memory cells within the solid-state memory, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level;
providing a behavior of at least some of the plurality of memory cells within the solid-state memory;
wherein the step of writing comprises writing to at least certain ones of the plurality of memory cells within the solid-state memory based on the provided behavior of the at least some of the memory cells within the solid-state memory, thereby writing to the at least certain ones of the plurality of memory cells within the solid-state memory in a non-uniform manner.
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Accused Products
Abstract
A method for intra-block wear leveling within solid-state memory subjected to wear, having a plurality of memory cells includes the step of writing to at least certain ones of the plurality of memory cells, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level. For example, if a behavior of at least some of the plurality of memory cells is not characterized, then the method may comprise characterizing a behavior of at least some of the plurality of memory cells and writing to at least certain ones of the plurality of memory cells, based on the characterized behavior, and in a non-uniform manner.
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Citations
18 Claims
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1. A method for intra-block wear leveling within solid-state memory subjected to wear, and having a plurality of memory cells arranged in blocks, the method comprising the step of:
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writing to at least certain ones of the plurality of memory cells within the solid-state memory, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level; providing a behavior of at least some of the plurality of memory cells within the solid-state memory; wherein the step of writing comprises writing to at least certain ones of the plurality of memory cells within the solid-state memory based on the provided behavior of the at least some of the memory cells within the solid-state memory, thereby writing to the at least certain ones of the plurality of memory cells within the solid-state memory in a non-uniform manner. - View Dependent Claims (2, 3, 4, 5)
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6. A computer program product for intra-block wear leveling within solid-state memory, the computer program product comprising:
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a non-transitory computer-readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising; computer readable program code configured to implement a method for intra-block wear leveling within solid-state memory subjected to wear, and having a plurality of memory cells arranged in blocks, the method comprising the step of; writing to at least certain ones of the plurality of memory cells within the solid-state memory, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level; and providing a behavior of at least some of the plurality of memory cells within the solid-state memory; wherein the step of writing comprises writing to at least certain ones of the plurality of memory cells within the solid-state memory based on the provided behavior of the at least some of the memory cells within the solid-state memory, thereby writing to the at least certain ones of the plurality of memory cells within the solid-state memory in a non-uniform manner. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A system, comprising:
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a computing network including a processing device in communication with one or more computer memory storage devices; and the computing network further configured to implement a method for intra-block wear leveling within solid-state memory subjected to wear, and having a plurality of memory cells arranged in blocks, the method comprising the steps of; writing to at least certain ones of the plurality of memory cells within the solid-state memory, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level; providing a behavior of at least some of the plurality of memory cells within the solid-state memory; wherein the step of writing comprises writing to at least certain ones of the plurality of memory cells within the solid-state memory based on the provided behavior of the at least some of the memory cells within the solid-state memory, thereby writing to the at least certain ones of the plurality of memory cells within the solid-state memory in a non-uniform manner. - View Dependent Claims (13, 14, 15, 16)
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17. A solid-state memory, comprising:
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a processor; a plurality of memory cells, where the processor is further configured to implement a method for intra-block wear leveling of at least some of the plurality of memory cells, the method further including the steps of writing to at least certain ones of the plurality of memory cells within the solid-state memory, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level; and providing a behavior of at least some of the plurality of memory cells within the solid-state memory; wherein the step of writing comprises writing to at least certain ones of the plurality of memory cells within the solid-state memory based on the provided behavior of the at least some of the memory cells within the solid-state memory, thereby writing to the at least certain ones of the plurality of memory cells within the solid-state memory in a non-uniform manner. - View Dependent Claims (18)
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Specification