Method and apparatus for storing data in a flash memory including single level memory cells and multi level memory cells

• US 8,495,320 B1
• Filed: 03/09/2012
• Issued: 07/23/2013
• Est. Priority Date: 07/22/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sheredy, Joseph, Nguyen, Lau
• Primary Examiner(s): Lam, David
• Application Number:
  US13/416,678
• Time in Patent Office: 501 Days
• Field of Search: 711/162, 711118-119, 711/103, 711112-114, 711132-136
• US Class Current: 711/162
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write-erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.

Claims

1. A method for storing data in a memory module including (i) a single-level cell memory block and (ii) a multi-level cell memory block, the method comprising:

storing the data in the memory module, and periodically updating the data stored in the memory module; and

based on the periodic updating of the data stored in the memory module, predicting a frequency at which the data stored in the memory module is to be updated,

wherein storing the data in the memory module further includes

based on the predicted frequency at which the data stored in the memory module is to be updated, storing the data in the single-level cell memory block or the multi-level cell memory block.

2. The method of claim 1, wherein storing the data in the single-level cell memory block or the multi-level cell memory block comprises:

in response to the predicted frequency at which the data stored in the memory module is to be updated being greater than a predetermined threshold, storing the data in the single-level cell memory block.

3. The method of claim 2, further comprising:

if the data is stored in the multi-level cell memory block prior to storing the data in the single-level cell memory block, erasing the data from the multi-level cell memory block prior to or subsequent to storing the data in the single-level cell memory block.

4. The method of claim 1, wherein storing the data in the single-level cell memory block or the multi-level cell memory block comprises:

in response to the predicted frequency at which the data stored in the memory module is to be updated being less than a predetermined threshold, storing the data in the multi-level cell memory block.

5. The method of claim 4, further comprising:

if the data is stored in the single-level cell memory block prior to storing the data in the multi-level cell memory block, erasing the data from the single-level cell memory block prior to or subsequent to storing the data in the multi-level cell memory block.

6. The method of claim 1, further comprising:

based on the predicted frequency at which the data stored in the memory module is to be updated, categorizing the data as either (i) a frequently updated data, or (ii) an infrequently updated data,

wherein storing the data in the memory module further includes

in response to the data being categorized as the frequently updated data, storing the data in the single-level cell memory block.

7. The method of claim 6, wherein storing the data in the memory module further includes:

in response to the data being categorized as the infrequently updated data, storing the data in the multi-level cell memory block.

8. A non-transient computer-readable storage medium having instructions tangibly stored thereon, the instructions for storing data in a memory module including (i) a single-level cell memory block and (ii) a multi-level cell memory block, the instructions being executable by a programmable processor to:

store the data in the memory module, and periodically update the data stored in the memory module; and

based on the periodic updating of the data stored in the memory module, predict a frequency at which the data stored in the memory module is to be updated,

wherein the instructions to store the data in the memory module further include instructions to

based on the predicted frequency at which the data stored in the memory module is to be updated, store the data in the single-level cell memory block or the multi-level cell memory block.

9. The non-transient computer-readable storage medium of claim 8, wherein the instructions to store the data in the single-level cell memory block or the multi-level cell memory block include instructions to:

in response to the predicted frequency at which the data stored in the memory module is to be updated being greater than a predetermined threshold, store the data in the single-level cell memory block.

10. The non-transient computer-readable storage medium of claim 8, wherein the instructions to store the data in the single-level cell memory block or the multi-level cell memory block include instructions to:

in response to the predicted frequency at which the data stored in the memory module is to be updated being less than a predetermined threshold, store the data in the multi-level cell memory block.

11. The non-transient computer-readable storage medium of claim 8, wherein the instructions being executable by the programmable processor is further to:

based on the predicted frequency at which the data stored in the memory module is to be updated, categorize the data as either (i) a frequently updated data, or (ii) an infrequently updated data,

wherein the instructions to store the data in the single-level cell memory block or the multi-level cell memory block include instructions to

in response to the data being categorized as the frequently updated data, store the data in the single-level cell memory block.

12. The non-transient computer-readable storage medium of claim 11, wherein the instructions to store the data in the single-level cell memory block or the multi-level cell memory block include instructions to:

in response to the data being categorized as the infrequently updated data, store the data in the multi-level cell memory block.

13. A cache system configured to be operatively coupled to a memory module that comprises (i) a single-level cell memory block and (ii) a multi-level cell memory block, the cache system comprising:

a memory cache; and

a cache controller configured to

store data in the memory module, and periodically update the data stored in the memory module, and

based on the periodic updating of the data stored in the memory module, predict a frequency at which the data stored in the memory module is to be updated,

wherein the cache controller is further configured to store the data in the memory module by, based on the predicted frequency at which the data stored in the memory module is to be updated, storing the data in the single-level cell memory block or the multi-level cell memory block.

14. The cache system of claim 13, wherein the cache controller is further configured to store the data in the memory module by, in response to the predicted frequency at which the data stored in the memory module is to be updated being greater than a predetermined threshold, storing the data in the single-level cell memory block.

15. The cache system of claim 14, wherein the cache controller is further configured to:

if the data is stored in the multi-level cell memory block prior to storing the data in the single-level cell memory block, erase the data from the multi-level cell memory block prior to or subsequent to storing the data in the single-level cell memory block.

16. The cache system of claim 13, wherein the cache controller is further configured to store the data in the memory module by, in response to the predicted frequency at which the data stored in the memory module is to be updated being less than a predetermined threshold, storing the data in the multi-level cell memory block.

17. The cache system of claim 16, wherein the cache controller is further configured to:

if the data is stored in the single-level cell memory block prior to storing the data in the multi-level cell memory block, erase the data from the single-level cell memory block prior to or subsequent to storing the data in the multi-level cell memory block.

18. The cache system of claim 13, wherein the cache controller is further configured to:

based on the predicted frequency at which the data stored in the memory module is to be updated, categorize the data as either (i) a frequently updated data, or (ii) an infrequently updated data;

in response to the data being categorized as the frequently updated data, store the data in the single-level cell memory block; and

in response to the data being categorized as the infrequently updated data, store the data in the multi-level cell memory block.