Controller for optimizing throughput of read operations

• US 8,495,332 B2
• Filed: 07/24/2009
• Issued: 07/23/2013
• Est. Priority Date: 07/24/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Wakrat, Nir Jacob, Khmelnitsky, Vadim, Post, Daniel Jeffrey
• Primary Examiner(s): Elmore, Reba I
• Application Number:
  US12/509,240
• Publication Number:
  US 20110022781A1
• Time in Patent Office: 1,460 Days
• Field of Search: 711/103, 711/135, 711/173, 711/202, 711/206
• US Class Current: 711/173
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

A controller, techniques, systems, and devices for optimizing throughput of read operations in flash memory are disclosed. Various optimizations of throughput for read operations can be performed using a controller. In some implementations, read operations for a multi-die flash memory device or system can be optimized to perform a read request with a highest priority (e.g., an earliest received read request) as soon as the read request is ready. In some implementations, the controller can enable optimized reading from multiple flash memory dies by monitoring a read/busy state for each die and switching between dies when a higher priority read operation is ready to begin.

Claims

1. A method comprising:

reading first data from a first flash memory die using an internal bus in response to a first read request;

pausing reading of the first data from the first flash memory die upon second data being ready to be read from a second flash memory die, where the second data is read from the second flash memory die in response to a second read request that has a higher priority than the first read request;

reading the second data from the second flash memory die using the internal bus; and

resuming reading of the first data from the first flash memory using the internal bus;

wherein the method further comprises;

storing the first data read from the first flash memory die in a first buffer, wherein a portion of the first data is stored in the first buffer before reading of the first data from the first flash memory die is paused and where a remaining portion of the first data is stored in the first buffer after the second data is read from the second flash memory die using the internal bus;

storing the second data read from the second flash memory die in a second buffer; and

checking the second data stored in the second buffer for errors.

2. The method of claim 1, further comprising:

transmitting the second data to a host that is external to a device containing the first and second flash memory dies using an external bus; and

transmitting the first data the host using the external bus, where the first data is transmitted to the host using the external bus after the second data is transmitted to the host using the external bus.

3. The method of claim 1, where the first flash memory die is different than the second flash memory die.

4. The method of claim 1, where a signal from the second flash memory die indicates that the second data is ready to be read from the second flash memory die.

5. The method of claim 1, where the second read request has a higher priority than the first read request based upon the second read request having been received before the first read request.

6. The method of claim 1, where reading of the first data from the first flash memory die resumes after the second data is read from the second flash memory die using the internal bus.

7. The method of claim 1, where the second data is ready to be read from the second flash memory die when at least a portion of the second data has been transferred to a register for the second flash memory die.

8. The method of claim 1, further comprising:

reading third data from the second flash memory die using the internal bus in response to a third read request, where the third data is read from the second flash memory die before the second data is read from the second flash memory die based upon the third read request having a higher priority than the second read request, where the third read request has a higher priority than the second read request based upon the third read request having been received before the second read request.

9. The method of claim 8, where reading the first data from the first flash memory die using the internal bus begins after the third data has been read from the second flash memory die using the internal bus.

10. The method of claim 8, further comprising:

instructing, using the internal bus, the second flash memory die to prepare the second data to be read from the second flash memory die after the third data has been read from the second flash memory die using the internal bus.

11. A system for optimizing memory read operations comprising:

a first flash memory die;

a second flash memory die that is different than the first flash memory die;

an external bus configured to receive read requests from a host for data stored in the first and second flash memory dies; and

a controller coupled to the external bus and configured to pause first data being read from the first flash memory die in response to a first read request when second data is ready to be read from the second flash memory die in response to a second read request, where the second read request has a higher priority than the first read request;

a plurality of buffers that are configured to store data being read from the first and second flash memory dies, wherein a first buffer of the plurality buffers stores a portion of the first data being read from the first flash memory die while the second data is read from the second flash memory die and stored in a second buffer of the plurality buffers, where a remaining portion of the first data is transferred to the first buffer after the second data has been read from the second flash memory die; and

wherein, the controller is further configured to check the second data stored in the second buffer for errors.

12. The system of claim 11, further comprising:

an internal bus connecting the controller to the first and second flash memory dies, where data is read from the first and second flash memory dies using the internal bus.

13. The system of claim 11:

wherein the second data is ready to be read from the second flash memory die when at least a portion of the second data has been transferred to a register for the second flash memory die.

14. The system of claim 11, where external bus is further configured to transfer data read from the first and second flash memory dies to the host, where the second data is transferred to the host using the external bus before the first data is transferred to the host using the external bus.

15. The system of claim 11, where the second read request has a higher priority than the first read request based upon the second read request having been received through the external bus before the first read request.

16. A flash memory device comprising:

a first flash memory die;

a second flash memory die that is different than the first flash memory die;

an external bus configured to receive read requests from a host for data stored in the first and second flash memory dies, where the host is external to the flash memory device; and

a controller coupled to the external bus and configured to pause first data being read from the first flash memory die in response to a first read request when second data is ready to be read from the second flash memory die in response to a second read request, where the second read request has a higher priority than the first read request;

a plurality of buffers that are configured to store data being read from the first and second flash memory dies, wherein a first buffer of the plurality buffers stores a portion of the first data being read from the first flash memory die while the second data is read from the second flash memory die and stored in a second buffer of the plurality buffers, where a remaining portion of the first data is transferred to the first buffer after the second data has been read from the second flash memory die; and

wherein, the controller is further configured to check the second data stored in the second buffer for errors.

17. The device of claim 16, further comprising:

an internal bus connecting the controller to the first and second flash memory dies, where data is read from the first and second flash memory dies using the internal bus.

18. The device of claim 16:

wherein the second data is ready to be read from the second flash memory die when at least a portion of the second data has been transferred to a register for the second flash memory die.

19. The device of claim 16, where external bus is further configured to transfer data read from the first and second flash memory dies to the host, where the second data is transferred to the host using the external bus before the first data is transferred to the host using the external bus.

20. The device of claim 16, where the second read request has a higher priority than the first read request based upon the second read request having been received through the external bus before the first read request.

21. A method comprising:

receiving a first request to read first data from a first flash memory die;

receiving a second request to read second data from the first flash memory die;

receiving a third request to read third data from a second flash memory die, where the first request has higher priority than the second and third requests, and where the second request has higher priority than the third request;

reading the first data from the first flash memory die using an internal bus;

storing the first data read from the first flash memory die in a first buffer;

instructing, using the internal bus, the first flash memory die to prepare the second data to be read from the first flash memory die;

reading the third data from second flash memory die using the internal bus;

storing the third data read from the second flash memory die in a second buffer;

pausing reading of the third data from the second flash memory die upon the second data being ready to be read from the first flash memory die;

reading the second data from the first flash memory die using the internal bus;

storing the second data read from the first flash memory die in a third buffer;

resuming reading of the third data from the second flash memory die;

resuming storing of the third data read from the second flash memory die in the second buffer; and

checking the second data stored in the third buffer for errors.

22. The method of claim 21, further comprising:

transmitting the first data read from the first flash memory die to an external host using an external bus;

transmitting the second data read from the first flash memory die to the external host using the external bus; and

transmitting the third data from the buffer to the external host using the external bus.