Translated memory protection
First Claim
Patent Images
1. A host computer system comprising:
- a first primitive operation generated from a first target instruction in a target program;
a second primitive operation generated from a second target instruction in said target program;
a translator configured to schedule said first primitive operation and said second primitive operation into an instruction of said host computer system; and
said translator also configured to provide an indication that said first and second target instructions have been translated into said first and second primitive operations.
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Accused Products
Abstract
A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.
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Citations
20 Claims
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1. A host computer system comprising:
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a first primitive operation generated from a first target instruction in a target program; a second primitive operation generated from a second target instruction in said target program; a translator configured to schedule said first primitive operation and said second primitive operation into an instruction of said host computer system; and said translator also configured to provide an indication that said first and second target instructions have been translated into said first and second primitive operations. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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generating a first primitive operation from a first target instruction in a target program; generating a second primitive operation from a second target instruction in said target program; scheduling said first primitive operation and said second primitive operation into a host instruction of a host computer system; and executing said host instruction on a host computer system, wherein said host computer is incapable of natively executing said first target instruction. - View Dependent Claims (9, 10, 11, 12)
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13. A host computer system comprising:
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means for generating a first primitive operation from a first target instruction in a target program; means for generating a second primitive operation from a second target instruction in said target program; means for scheduling said first primitive operation and said second primitive operation into a host instruction of a host computer system; and means for executing said host instruction on a host computer system, wherein said host computer is incapable of natively executing said first target instruction. - View Dependent Claims (14, 15, 16)
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17. An article of manufacture including a non-transitory computer readable medium having instructions stored thereon that, responsive to execution by a computing device, cause the computing device to perform operations comprising:
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generating a first primitive operation from a first target instruction in a target program; generating a second primitive operation from a second target instruction in said target program; scheduling said first primitive operation and said second primitive operation into a host instruction of a host computer system; and executing said host instruction on a host computer system, wherein said host computer is incapable of natively executing said first target instruction. - View Dependent Claims (18, 19, 20)
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Specification