Instruction length based cracking for instruction of variable length storage operands

• US 8,495,341 B2
• Filed: 02/17/2010
• Issued: 07/23/2013
• Est. Priority Date: 02/17/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Busaba, Fadi, Curran, Brian, Giamei, Bruce, Jacobi, Christian, Li, Wen
• Primary Examiner(s): LI, AIMEE J
• Application Number:
  US12/707,163
• Publication Number:
  US 20110202747A1
• Time in Patent Office: 1,252 Days
• Field of Search: 712/204, 712/210, 712/225
• US Class Current: 712/210
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros

Abstract

A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.

Claims

1. A method for managing variable operand length instructions, the method comprising:

receiving at least one variable operand length instruction;

analyzing the at least one variable operand length instruction;

identifying, based on the analyzing, a length of at least one operand in the variable operand length instruction;

organizing, during at least one of instructing decoding cycles and instruction grouping cycles, the at least one variable operand length instruction into a set of unit of operations, wherein a different organization is performed for different lengths of the at least one operand, and wherein the set of unit of operations are issuable and executable in parallel;

sending the set of unit of operations to an instruction sequencing unit;

issuing, by the instruction sequencing unit, the set of unit of operations to one or more execution units; and

executing, by the one or more execution units, the set of unit of operations.

2. The method of claim 1, wherein the at least one variable operand length instruction is one of a storage-to-storage logical instruction and a storage-to-storage decimal instruction.

3. The method of claim 1, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into a first unit of operation and a second unit of operation, wherein the first unit of operation fetches a given number of bytes from an operand associated with the variable operand length instruction and stores the given number of bytes into a scratch general register, and

wherein the second unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the second unit of operation calculates a storage address and performs pretesting on the storage address, wherein the second unit of operation reads the given number of bytes from the scratch general register and sends the given number of bytes to a store buffer unit where data is to be stored to memory.

4. The method of claim 1, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into a first unit of operation, a second unit of operation, a third unit of operation, and a fourth unit of operation, wherein the first unit of operation fetches a first given number of bytes from an operand associated with the variable operand length instruction and stores the first given number of bytes into a first scratch general register,

wherein the second unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the second unit of operation calculates a first storage address and performs pretesting on the first storage address, wherein the second unit of operation reads the first given number of bytes from the first scratch general register and sends the first given number of bytes to a store buffer unit,

wherein the third unit of operation fetches a second given number of bytes from the operand and stores the second given number of bytes into a second scratch general register, and

wherein the fourth unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the fourth unit of operation calculates a second storage address and performs pretesting on the second storage address, wherein the second unit of operation reads the second given number of bytes from the second scratch general register and sends the second given number of bytes to the store buffer unit where data is to be stored in memory.

5. The method of claim 1, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into a first unit of operation and a second unit of operation, wherein the first unit of operation fetches a given number of bytes from a first operand associated with the variable length instruction and stores the given number of bytes into a scratch general register, and

wherein the second unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the second unit of operation calculates a storage address and performs pretesting on the storage address, wherein the second unit of operation fetches a given number of bytes from a second operand and passes the given number of bytes from the second operand to the fixed-point unit, and wherein the fixed-point unit performs an operation comprising one of an exclusive OR operation, an OR operation, and an AND operation on the given number of bytes from the scratch general register and the given number of bytes from the second operand and sets a condition code based on a result of the operation, and wherein the fixed point unit sends the result back to the load store unit to be stored in memory at a location associated with the first operand.

6. The method of claim 1, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into a first unit of operation and a second unit of operation, wherein the first unit of operation fetches a given number of bytes from a first operand associated with the variable operand length instruction and stores the given number of bytes into a scratch general register, and

wherein the second unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the second unit of operation calculates a storage address and performs pretesting on the storage address, wherein the second unit of operation fetches a given number of bytes from a second operand and passes the given number of bytes from the second operand to the fixed-point unit, and wherein the fixed-point unit compares the given number of bytes from the scratch general register and the given number of bytes from the second operand and sets a condition code based thereon.

7. The method of claim 1, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into at a first unit of operation, a second unit of operation, a third unit of operation, and a fourth unit of operation, wherein the first unit of operation fetches a given number of bytes from a first operand associated with the variable length instruction and stores the given number of bytes into a first scratch register,

wherein the second unit of operation fetches a given number of bytes from a second operand associated with the variable operand length instruction and stores the given number of bytes into a second scratch register,

wherein the third unit of operation is executed in the decimal point floating unit and performs a decimal point unit operation on the given number of bytes in the first scratch register and the given number of bytes in the second scratch register and stores a resultant dataset in the first scratch register, and

wherein the fourth unit of operation reads the first scratch register and sends the resultant dataset to memory to be stored at location associated with the first operand.

8. The method of claim 1, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into at least a first unit of operation, a second unit of operation, a third unit of operation, a fourth operation, a fifth unit of operation, and a sixth unit of operation, wherein the first unit of operation fetches a first given number of bytes from a first operand associated with the variable length instruction and stores the first given number of bytes into a first scratch register,

wherein the second unit of operation fetches a second given number of bytes from the first operand and stores the second given number of bytes into a second scratch register,

wherein the third unit of operation fetches a given number of bytes from a second operand associated with the variable operand length instruction and stores the given number of bytes into a third scratch register,

wherein the fourth unit of operation is executed in the decimal point floating unit and performs a decimal point unit operation on the given number of bytes in the first and second scratch registers and the given number of bytes in the third scratch register,

wherein the fifth unit of operation sends a first resultant dataset from the decimal point unit of operation to memory to be stored at a location associated with the first operand, and

wherein the sixth unit of operation sends a second resultant dataset from the decimal point unit of operation to memory to be stored at a location associated with the first operand.

9. The method of claim 1, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into at least a first unit of operation, a second unit of operation, a third unit of operation, a fourth unit of operation, and a fifth unit of operand, wherein the first unit of operation fetches a given number of bytes from a first operand associated with the variable length instruction and stores the given number of bytes into a first scratch register,

wherein the second unit of operation fetches a first given number of bytes from a second operand associated with the variable length instruction and stores the first given number of bytes into a second scratch register,

wherein the third unit of operation fetches a second given number of bytes from the second operand and stores the second given number of bytes into a third scratch register,

wherein the fourth unit of operation is executed in the decimal point floating unit and performs a decimal point unit operation on the given number of bytes in the first scratch register and the first and second given number of bytes in the second and third registers and saves a resultant dataset back in the first scratch register, and

wherein the fifth unit of operation reads a resultant dataset of the decimal point operation from the first scratch register and sends the resultant dataset of memory to be saved at a location associated with the first operand.

10. The method of claim 1, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into at least a first unit of operation, a second unit of operation, a third unit of operation, a fourth unit of operation, a fifth unit of operation, a sixth unit of operation, and a seventh unit of operation, wherein the first unit of operation fetches a first given number of bytes from a first operand associated with the variable operand length instruction and stores the first given number of bytes into a first scratch register,

wherein the second unit of operation fetches a second given number of bytes from the first operand and stores the second given number of bytes into a second scratch register,

wherein the third unit of operation fetches a first given number of bytes from a second operand associated with the variable operands length instruction and stores the first given number of bytes into a third scratch register,

wherein the fourth unit of operation fetches a second given number of bytes from the second operand and stores the second given number of bytes into a fourth scratch register,

wherein the fifth unit of operation is executed in the decimal point floating unit and performs a decimal point unit operation on the given number of bytes in the first and second scratch registers and the given number of bytes in the third and fourth registers,

wherein the sixth unit of operation sends a first resultant dataset from the decimal point unit of operation to memory to be stored at a location associated with the first operand, and

wherein the seventh unit of operation sends a second resultant dataset from the decimal point unit of operation to memory to be stored at a location associated with the first operand.

11. An information processing system for managing variable operand length instructions, the information processing system comprising:

a memory;

a processor communicatively coupled to the memory, wherein the processor comprises at least a cracking unit, an instruction decoding unit, an instruction sequencing unit, and one or more execution units,

wherein the cracking unit is configured to perform a method comprising;

receiving at least one variable operand length instruction;

analyzing the at least one variable operand length instruction;

identifying, based on the analyzing, a length of at least one operand in the variable operand length instruction; and

determining, based on the identifying, if the length of the at least one operand satisfies a threshold;

based on the length of the at least one operand satisfying the threshold, the method further comprises;

organizing, during at least one of instructing decoding cycles and instruction grouping cycles, the at least one variable operand length instruction into a set of unit of operations, wherein a different organization is performed for different lengths of the at least one operand, and wherein the set of unit of operations are issuable and executable in parallel;

wherein the instruction decoding unit is configured to perform a method comprising;

sending the set of unit of operations to the instruction sequencing unit based on the length of the at least one operand satisfying the threshold; and

sending the least one variable operand length instruction to the instruction sequencing unit based on the length of the at least one operand failing to satisfy the threshold;

wherein the instruction sequencing unit is configured to perform a method comprising;

issuing the set of unit of operations to the one or more execution units based on the length of the at least one operand satisfying the threshold; and

issuing the least one variable operand length instruction to the one or more execution units as a sequenced instruction based on the length of the at least one operand failing to satisfy the threshold; and

wherein the one or more execution units are configured to perform a method comprising;

executing the set of unit of operations based on the length of the at least one operand satisfying the threshold; and

executing the sequenced instruction based on the length of the at least one operand failing to satisfy the threshold.

12. The information processing system of claim 11, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into a first unit of operation and a second unit of operation, wherein the first unit of operation fetches a given number of bytes from an operand associated with the variable operand length instruction and stores the given number of bytes into a scratch general register, and

wherein the second unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the second unit of operation calculates a storage address and performs pretesting on the storage address, wherein the second unit of operation reads the given number of bytes from the scratch general register and sends the given number of bytes to a store buffer unit where data is to be stored to memory.

13. The information processing system of claim 11, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into a first unit of operation, a second unit of operation, a third unit of operation, and a fourth unit of operation, wherein the first unit of operation fetches a first given number of bytes from an operand associated with the variable operand length instruction and stores the first given number of bytes into a first scratch general register,

wherein the second unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the second unit of operation calculates a first storage address and performs pretesting on the first storage address, wherein the second unit of operation reads the first given number of bytes from the first scratch general register and sends the first given number of bytes to a store buffer unit,

wherein the third unit of operation fetches a second given number of bytes from the operand and stores the second given number of bytes into a second scratch general register, and

wherein the fourth unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the fourth unit of operation calculates a second storage address and performs pretesting on the second storage address, wherein the second unit of operation reads the second given number of bytes from the second scratch general register and sends the second given number of bytes to the store buffer unit where data is to be stored in memory.

14. The information processing system of claim 11, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into a first unit of operation and a second unit of operation, wherein the first unit of operation fetches a given number of bytes from a first operand associated with the variable length instruction and stores the given number of bytes into a scratch general register, and

wherein the second unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the second unit of operation calculates a storage address and performs pretesting on the storage address, wherein the second unit of operation fetches a given number of bytes from a second operand and passes the given number of bytes from the second operand to the fixed-point unit, and wherein the fixed-point unit performs an operation comprising one of an exclusive OR operation, an OR operation, and an AND operation on the given number of bytes from the scratch general register and the given number of bytes from the second operand and sets a condition code based on a result of the operation, and wherein the fixed point unit sends the result back to the load store unit to be stored in memory at a location associated with the first operand.

15. The information processing system of claim 11, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into a first unit of operation and a second unit of operation, wherein the first unit of operation fetches a given number of bytes from a first operand associated with the variable operand length instruction and stores the given number of bytes into a scratch general register, and

wherein the second unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the second unit of operation calculates a storage address and performs pretesting on the storage address, wherein the second unit of operation fetches a given number of bytes from a second operand and passes the given number of bytes from the second operand to the fixed-point unit, and wherein the fixed-point unit compares the given number of bytes from the scratch general register and the given number of bytes from the second operand and sets a condition code based thereon.

16. A computer program product for managing variable operand length instructions, the computer program product comprising:

a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

receiving at least one variable operand length instruction;

analyzing the at least one variable operand length instruction;

identifying, based on the analyzing, a length of at least one operand in the variable operand length instruction;

organizing, during at least one of instructing decoding cycles and instruction grouping cycles, the at least one variable operand length instruction into a set of unit of operations, wherein a different organization is performed for different lengths of the at least one operand, and wherein the set of unit of operations are issuable and executable in parallel;

sending the set of unit of operations to an instruction sequencing unit;

issuing, by the instruction sequencing unit, the set of unit of operations to one or more execution units; and

executing, by the one or more execution units, the set of unit of operations.

17. The computer program product of claim 16, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into a first unit of operation, a second unit of operation, a third unit of operation, and a fourth unit of operation, wherein the first unit of operation fetches a first given number of bytes from an operand associated with the variable operand length instruction and stores the first given number of bytes into a first scratch general register,

wherein the second unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the second unit of operation calculates a first storage address and performs pretesting on the first storage address, wherein the second unit of operation reads the first given number of bytes from the first scratch general register and sends the first given number of bytes to a store buffer unit,

wherein the third unit of operation fetches a second given number of bytes from the operand and stores the second given number of bytes into a second scratch general register, and

wherein the fourth unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the fourth unit of operation calculates a second storage address and performs pretesting on the second storage address, wherein the second unit of operation reads the second given number of bytes from the second scratch general register and sends the second given number of bytes to the store buffer unit where data is to be stored in memory.

18. The computer program product of claim 16, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into a first unit of operation and a second unit of operation, wherein the first unit of operation fetches a given number of bytes from a first operand associated with the variable length instruction and stores the given number of bytes into a scratch general register, and

wherein the second unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the second unit of operation calculates a storage address and performs pretesting on the storage address, wherein the second unit of operation fetches a given number of bytes from a second operand and passes the given number of bytes from the second operand to the fixed-point unit, and wherein the fixed-point unit performs an operation comprising one of an exclusive OR operation, an OR operation, and an AND operation on the given number of bytes from the scratch general register and the given number of bytes from the second operand and sets a condition code based on a result of the operation, and wherein the fixed point unit sends the result back to the load store unit to be stored in memory at a location associated with the first operand.

19. The computer program product of claim 16, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into a first unit of operation and a second unit of operation, wherein the first unit of operation fetches a given number of bytes from a first operand associated with the variable operand length instruction and stores the given number of bytes into a scratch general register, and

wherein the second unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the second unit of operation calculates a storage address and performs pretesting on the storage address, wherein the second unit of operation fetches a given number of bytes from a second operand and passes the given number of bytes from the second operand to the fixed-point unit, and wherein the fixed-point unit compares the given number of bytes from the scratch general register and the given number of bytes from the second operand and sets a condition code based thereon.

20. The computer program product of claim 16, wherein organizing the at least one variable operand length instruction into a set of unit of operations comprises:

organizing the at least one variable operand length instruction into a first unit of operation and a second unit of operation, wherein the first unit of operation fetches a given number of bytes from an operand associated with the variable operand length instruction and stores the given number of bytes into a scratch general register, and

wherein the second unit of operation is issued to a load-store unit and to a fixed-point unit, and wherein the second unit of operation calculates a storage address and performs pretesting on the storage address, wherein the second unit of operation reads the given number of bytes from the scratch general register and sends the given number of bytes to a store buffer unit.