Technique for memory imprint reliability improvement

• US 8,495,438 B2
• Filed: 09/08/2008
• Issued: 07/23/2013
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Roine, Per Torstein
• Primary Examiner(s): LOHN, JOSHUA A
• Application Number:
  US12/205,976
• Publication Number:
  US 20090172496A1
• Time in Patent Office: 1,779 Days
• Field of Search: 714/719, 714/701, 711/106, 365/222
• US Class Current: 714/719
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/451 using a set of candidate code words, e.g. ordered statistics decoding [OSD]

Abstract

One embodiment of the present invention relates to a method of reducing imprint of a memory cell. The method comprises adding an inversion condition bit operably associated with one or more memory cells storing a memory word. The inversion condition bit indicates whether the memory word represents an actual payload or an inversion of the actual payload. The inversion condition bit and memory word are selectively toggled by a control circuitry. Inversion is performed by reading the inversion condition bit and memory word and rewriting the memory word back to the one or more memory cells in an inverted or non-inverted state, depending on an inversion condition bit. The inversion condition bit is then written to the inversion status bit value. The memory address is incremented, and the inversion status data state is toggled once the address counter addresses the entire memory array. Other methods and circuits are also disclosed.

Claims

1. A method, comprising:

storing a data value in a memory word comprising one or more memory cells;

storing an inversion condition bit in a memory location operably associated with the memory word, wherein the inversion condition bit indicates if the associated memory word currently stores an actual data value or an inverted data value;

providing an inversion status bit that comprises information associated with an inversion status of the memory array;

providing an address counter value from an address counter configured to advance through a plurality of address counter values, so that each memory word in the memory array is associated with a particular address counter value;

reading the data value and the inversion condition bit from the memory location associated with the address counter value;

inverting the data value

inverting the inversion condition bit;

re-writing the inverted data value and the inverted inversion condition bit to the memory location associated with the address counter value;

incrementing the address counter value; and

toggling the inversion status bit and resetting the address counter to the lowest numbered memory address once the memory address counter has addressed the plurality of memory addresses;

providing a control circuitry by which an error correction code (an ECC) can be implemented;

storing at least one ECC syndrome bit and a parity bit in a first additional memory location; and

a read operation of the method comprising;

reading the data value, the inversion condition bit, and the at least one ECC syndrome bit;

correcting single bit errors and detecting double bit errors using ECC;

storing an address associated with an uncorrectable double error bit in a second additional memory location;

performing a first round of error correction if an error is detected, the first round of error correction comprising selectively inverting the data value, the inversion condition bit, and the at least one ECC syndrome bit until a single bit error is corrected or all inversion condition bit combinations are exhausted;

performing a second round of error correction if the error is still detected, wherein the second round of error correction comprises selectively inverting the data value, the inversion condition bit, and the at least one ECC syndrome bit until a single bit error is corrected or all inversion condition bit combinations are exhausted;

storing an address associated with an uncorrectable double error bit in the second additional memory location;

incrementing the memory address counter;

toggling the inversion status bit once the memory address counter has addressed the plurality of memory addresses; and

writing an memory address counter value and the toggled inversion status bit to memory.

2. The method of claim 1, further comprising:

comparing the address counter value with an address of a memory location to be written;

operating a logic function on a result of the comparison and the inversion status bit to determine if inversion of data to be written is needed; and

inverting the data to be written data and writing the inverted data and an inversion condition bit indicating that the memory word is inverted to the addressed memory location;

or

writing the data to be written and an inversion condition bit indicating the memory word is not inverted to the addressed memory location.

3. The method of claim 1, further comprising:

reading a data value and a corresponding inversion condition bit from the addressed memory location; and

outputting either the data value or the inverted data value, depending on the value of the inversion condition bit.

4. The method of claim 1, further comprising:

comparing an address of the memory word with the memory word address from the memory address counter;

operating a logic function on a result of the comparison and the inversion status bit, resulting in an output data value, an output inversion condition bit, and an output at least one ECC syndrome bit;

performing a first round of error correction if an error is found, the first round of error correction comprising selectively inverting the data value, the inversion condition bit, and the at least one ECC syndrome bit until a single bit error is corrected or all inversion condition bit combinations are exhausted;

performing a second round of error correction if the error is still found, wherein the second round of error correction comprises selectively inverting the data value, the inversion condition bit, and the at least one ECC syndrome bit until a single bit error is corrected or all inversion condition bit combinations are exhausted; and

storing an address associated with an uncorrectable double error bit in a second additional memory location.

5. The method of claim 1, further comprising storing a record of a failing bit of the ECC in a third additional memory location, wherein the record of failing bits comprises a memory word address of the memory bit, a position of the failing bit, and a value of the failing bit.

6. The method of claim 5, further comprising:

comparing the memory word address to the record of failing bits; and

performing the method of claim 4, if there is no match between addresses;

or

writing the inversion condition bit so that the failing bit is written to its potential stuck at value, if there is a match.

7. A method comprising:

storing a data value in one or more memory cells, the one or more memory cells comprising a memory word;

storing an inversion status bit in a memory location operably associated with the memory word, wherein the inversion status bit indicates if the memory word has been inverted;

providing an inversion pending bit in indicative of whether inversion of the memory word has taken place;

providing an address counter value from an address counter configured to advance through a plurality of address counter values, so that each memory word in the memory array is associated with a particular address counter value;

reading the data value;

setting the inversion pending bit to a data state indicating inversion of the data value is in progress;

writing the inversion status bit, the memory word address, the inversion pending bit, and at least one bit of the data value as one word a fourth additional memory location;

inverting the data value;

re-writing the inverted data value to the one or more memory cells;

setting the inversion pending bit to a data state indicating inversion of the data value is not in progress;

incrementing the address counter value;

toggling the inversion status once the address counter has addressed the plurality of memory addresses; and

writing the inversion status bit, the memory word address, and the inversion pending bit as one word to the fourth additional memory location.

8. The method of claim 7, further comprising:

comparing the address counter value with the memory word address;

operating a logic function on a result of the comparison and the inversion status bit to determine if inversion of a data value to be written is needed; and

inverting the data value to be written data and writing the inverted data value to the memory word address;

or

writing the data to be written to the memory word address.

9. The method of claim 7, further comprising:

reading the data value and the inversion condition bit;

comparing the address counter value with the memory word address;

operating a logic function on a result of the comparison and the inversion status bit to determine if inversion of a data value to be written is needed; and

inverting the data value to be written and outputting the inverted data value;

or

outputting the inverted data value.