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Technique for memory imprint reliability improvement

  • US 8,495,438 B2
  • Filed: 09/08/2008
  • Issued: 07/23/2013
  • Est. Priority Date: 12/28/2007
  • Status: Active Grant
First Claim
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1. A method, comprising:

  • storing a data value in a memory word comprising one or more memory cells;

    storing an inversion condition bit in a memory location operably associated with the memory word, wherein the inversion condition bit indicates if the associated memory word currently stores an actual data value or an inverted data value;

    providing an inversion status bit that comprises information associated with an inversion status of the memory array;

    providing an address counter value from an address counter configured to advance through a plurality of address counter values, so that each memory word in the memory array is associated with a particular address counter value;

    reading the data value and the inversion condition bit from the memory location associated with the address counter value;

    inverting the data valueinverting the inversion condition bit;

    re-writing the inverted data value and the inverted inversion condition bit to the memory location associated with the address counter value;

    incrementing the address counter value; and

    toggling the inversion status bit and resetting the address counter to the lowest numbered memory address once the memory address counter has addressed the plurality of memory addresses;

    providing a control circuitry by which an error correction code (an ECC) can be implemented;

    storing at least one ECC syndrome bit and a parity bit in a first additional memory location; and

    a read operation of the method comprising;

    reading the data value, the inversion condition bit, and the at least one ECC syndrome bit;

    correcting single bit errors and detecting double bit errors using ECC;

    storing an address associated with an uncorrectable double error bit in a second additional memory location;

    performing a first round of error correction if an error is detected, the first round of error correction comprising selectively inverting the data value, the inversion condition bit, and the at least one ECC syndrome bit until a single bit error is corrected or all inversion condition bit combinations are exhausted;

    performing a second round of error correction if the error is still detected, wherein the second round of error correction comprises selectively inverting the data value, the inversion condition bit, and the at least one ECC syndrome bit until a single bit error is corrected or all inversion condition bit combinations are exhausted;

    storing an address associated with an uncorrectable double error bit in the second additional memory location;

    incrementing the memory address counter;

    toggling the inversion status bit once the memory address counter has addressed the plurality of memory addresses; and

    writing an memory address counter value and the toggled inversion status bit to memory.

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