Array substrate and method of fabricating the same

• US 8,497,147 B2
• Filed: 05/25/2011
• Issued: 07/30/2013
• Est. Priority Date: 05/28/2010
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Seo, Hyun-Sik, Bae, Jong-Uk, Ryoo, Chang-Il
• Primary Examiner(s): MENZ, DOUGLAS M
• Application Number:
  US13/115,733
• Publication Number:
  US 20110291096A1
• Time in Patent Office: 797 Days
• Field of Search: 438/34, 438/85
• US Class Current: 438/34
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A method of fabricating an array substrate and a display device including the array substrate are discussed. According to an embodiment, the method includes forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer and an etch prevention layer on the gate insulating layer using a single mask, forming source and drain electrodes on the etch prevention layer, and forming a passivation layer including a contact hole on the source and drain electrodes and on the gate insulating layer, and forming a pixel electrode on the passivation layer and through the contact hole.

Claims

1. A method of fabricating an array substrate, comprising:

forming a gate electrode on a substrate;

forming a gate insulating layer on the gate electrode;

forming an oxide semiconductor layer and an etch prevention layer on the gate insulating layer using a single mask;

forming source and drain electrodes on the etch prevention layer; and

forming a passivation layer including a contact hole on the source and drain electrodes and on the gate insulating layer; and

forming a pixel electrode on the passivation layer and through the contact hole.

2. The method according to claim 1, wherein the step of forming the oxide semiconductor layer and the etch prevention layer includes:

forming an oxide semiconductor layer material on the gate insulating layer;

turning an upper portion of the oxide semiconductor layer material into an etch prevention material layer; and

patterning the oxide semiconductor layer material and the etch prevention material layer using the single mask to form the oxide semiconductor layer and the etch prevention layer.

3. The method according to claim 2, wherein the turning step includes applying a plasma treatment on the oxide semiconductor layer material.

4. The method according to claim 3, wherein the plasma treatment involves applying a sulfur hexafluoride (SF₆) and oxygen (O₂) plasma.

5. The method according to claim 1, wherein the step of forming the oxide semiconductor layer and the etch prevention layer includes:

forming the oxide semiconductor layer on the gate insulating layer using the single mask; and

turning an upper portion of the oxide semiconductor layer into the etch prevention layer.

6. The method according to claim 5, wherein the turning step includes applying a plasma treatment on the oxide semiconductor layer.

7. The method according to claim 6, wherein the plasma treatment involves applying a sulfur hexafluoride (SF₆) and oxygen (O₂) plasma.

8. The method according to claim 1, wherein the steps of the method are performed using five mask processes.

9. The method according to claim 1, wherein the array substrate is an array substrate of a liquid crystal display device or an array substrate of an organic electroluminescent display device.

10. The method according to claim 1, wherein the etch prevention layer has a thickness of approximately 1 to 20 nanometers.