MEMS devices and methods of forming same

• US 8,497,148 B2
• Filed: 07/22/2011
• Issued: 07/30/2013
• Est. Priority Date: 07/22/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chou, Bruce C. S.
• Primary Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US13/189,057
• Publication Number:
  US 20130020718A1
• Time in Patent Office: 739 Days
• Field of Search: 257/E21.001, 438/48, 438/50, 438/53, 438/98
• US Class Current: 438/48
• CPC Class Codes: B81B 2203/0307 Anchors
• CPC Class Codes: B81B 2203/04 Electrodes
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 3/0018 Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
• CPC Class Codes: B81C 1/00476 removing a sacrificial layer B81C1/00912 takes precedence
• CPC Class Codes: B81C 1/00801 Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer B81C1/00595, B81C1/00468 take precedence
• CPC Class Codes: B81C 2201/0109 Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13138 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/80011 Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/80012 Mechanical cleaning, e.g. abrasion using hydro blasting, brushes, ultrasonic cleaning, dry ice blasting, gas-flow
• CPC Class Codes: H01L 2224/80013 Plasma cleaning
• CPC Class Codes: H01L 2224/80031 by chemical means, e.g. etching, anodisation
• CPC Class Codes: H01L 2224/80047 by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 2224/8009 Vacuum
• CPC Class Codes: H01L 2224/80092 Atmospheric pressure
• CPC Class Codes: H01L 2224/80931 by chemical means, e.g. etching
• CPC Class Codes: H01L 2224/81002 being a removable or sacrificial coating
• CPC Class Codes: H01L 2224/81007 involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
• CPC Class Codes: H01L 2224/811 : the bump connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Claims

1. A method of forming a MEMS device comprising:

forming an isolation layer atop a substrate;

forming a sacrificial layer atop the isolation layer;

forming a first opening through the sacrificial layer;

bonding a wafer to the sacrificial layer;

forming a second opening extending through the wafer and aligned with the first opening;

filling the first opening and the second opening with a conductor stack;

forming a contact atop the conductor stack;

forming an etch hole through the wafer to expose the sacrificial layer; and

etching at least a portion of the sacrificial layer to form a cavity under a region of the wafer.

2. The method of claim 1, wherein filling the first opening and the second opening with a conductor stack comprises:

blanket depositing polysilicon over the wafer and in the first opening and the second opening; and

removing at least a portion of the polysilicon extending atop the wafer.

3. The method of claim 2 wherein removing at least a portion of the polysilicon extending atop the wafer comprises a process selected from a group consisting essentially of an etch back process, a chemical mechanical polish process, and combinations thereof.

4. The method of claim 1 further comprising forming an anchor electrode on the isolation layer, wherein the first opening and the second opening is aligned with the anchor electrode and further wherein the conductor electrically contacts the anchor electrode.

5. The method of claim 1 wherein forming an isolation layer comprises depositing a silicon nitride material by low pressure chemical vapor deposition.

6. The method of claim 1 wherein the sacrificial layer is an oxide and wherein etching at least a portion of the sacrificial layer comprises subjecting the sacrificial layer to an HF vapor etch.

7. The method of claim 1 wherein the conductor stack acts as an etch stop to prevent undercutting during the step of etching at least a portion of the sacrificial layer.

8. The method of claim 1 wherein the step of bonding a wafer to the sacrificial layer comprises fusion bonding.

9. The method of claim 8 further comprising annealing the wafer and sacrificial layer after the fusion bonding.

10. The method of claim 1 wherein the isolation layer has a high etch selectivity relative the sacrificial layer.

11. A method of forming a MEMS device, comprising:

forming an isolation layer on top of a substrate;

forming on top of the isolation layer a sacrificial oxide layer having a flat top surface;

forming an oxide opening in the sacrificial oxide layer;

bonding a silicon wafer layer to the sacrificial oxide layer;

opening a MEMS via in the silicon wafer layer aligned with the oxide opening in the sacrificial oxide layer;

filling the aligned MEMS via and the oxide opening with conductor material to form a polysilicon stack;

forming an etch hole through the silicon wafer layer; and

forming a cavity beneath the silicon wafer layer by removing the sacrificial oxide layer under a portion of the silicon wafer layer.

12. The method of claim 11, further comprising:

forming a conductor layer between the sacrificial oxide layer and the isolation layer, the conductor layer comprising an anchor area and a sensing electrode area.

13. The method of claim 11, wherein bonding the silicon wafer layer to the sacrificial oxide layer is performed at least in part by fusion bonding.

14. The method of claim 13, further comprising annealing the wafer and the sacrificial oxide layer after the fusion bonding.

15. The method of claim 11, wherein forming an isolation layer comprises depositing a silicon nitride material by low pressure chemical vapor deposition.

16. The method of claim 11, wherein removing the sacrificial oxide layer comprises subjecting the sacrificial oxide layer to an HF vapor etch.

17. The method of claim 11, wherein the polysilicon stack acts as an etch stop to prevent undercutting during the step of removing the sacrificial oxide layer.

18. A method of forming a MEMS device, comprising:

forming an isolation layer on top of a substrate;

forming an anchor electrode on the isolation layer;

forming on top of the isolation layer and the anchor electrode a sacrificial oxide layer having a flat top surface;

forming an oxide opening in the sacrificial oxide layer, reaching the anchor electrode;

bonding a silicon wafer layer to the sacrificial oxide layer;

thinning the silicon wafer layer;

opening a MEMS via in the silicon wafer layer aligned with the oxide opening in the sacrificial oxide layer;

filling the aligned MEMS via and the oxide opening with conductor material to form a polysilicon stack in touch with the anchor electrode;

forming an etch hole through the silicon wafer layer; and

forming a cavity beneath the silicon wafer layer by removing the sacrificial oxide layer under a portion of the silicon wafer layer.

19. The method of claim 18, wherein forming the polysilicon stack comprises:

blanket depositing polysilicon over the wafer and in the opening; and

removing at least a portion of the polysilicon extending atop the wafer.

20. The method of claim 18, wherein removing at least a portion of the polysilicon extending atop the wafer comprises a process selected from a group consisting essentially of an etch back process, a chemical mechanical polish process, and combinations thereof.