FinFET method and structure with embedded underlying anti-punch through layer

• US 8,497,171 B1
• Filed: 07/05/2012
• Issued: 07/30/2013
• Est. Priority Date: 07/05/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Goto, Ken-Ichi, Wu, Zhiqiang, Wu, Wei-Hao, Yang, Kai-Chieh, Hsieh, Wen-Hsing
• Primary Examiner(s): Picardat, Kevin M
• Application Number:
  US13/541,806
• Time in Patent Office: 390 Days
• Field of Search: 438/199, 438/218, 438/219, 438/221, 438/294, 438/296, 438/424
• US Class Current: 438/218
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods and structures for forming semiconductor FinFET devices with superior repeatability and reliability include providing APT (anti-punch through) layer accurately formed beneath a semiconductor fins, are provided. Both the n-type and p-type APT layers are formed prior to the formation of the material from which the semiconductor fin is formed. In some embodiments, barrier layers are added between the accurately positioned APT layer and the semiconductor fin. Ion implantation methods and epitaxial growth methods are used to form appropriately doped APT layers in a semiconductor substrate surface. The fin material is formed over the APT layers using epitaxial growth/deposition methods.

Claims

1. A method for forming a semiconductor device, comprising:

separately forming n-type and p-type anti-punch through (APT) layers over or in a substrate surface, said n-type and p-type APT layers not overlapping one another;

forming fin material over said n-type and p-type APT layers by epitaxial growth of undoped silicon;

forming a masking pattern over said fin material, said masking pattern defining covered portions and uncovered portions;

etching said uncovered portions thereby removing said fin material, said n-type and p-type APT layers and extending into said substrate to form discrete fins from said fin material; and

forming shallow trench isolation (STI) structures between said discrete fins.

2. The method as in claim 1, wherein said n-type and p-type APT layers are formed in said substrate surface by ion implantation.

3. The method as in claim 2, wherein said n-type APT layer includes Si and at least one of B, BF₂, and In, and said p-type APT layer includes Si and at least one of P and As.

4. The method as in claim 1, wherein said substrate is silicon and said n-type and p-type APT layers are formed over said substrate surface using epitaxial growth.

5. The method as in claim 4, wherein said n-type APT layer includes Si and at least one of B, BF₂, and In and said p-type APT layer includes Si and at least one of P and As.

6. The method as in claim 1, further comprising forming a barrier layer between said n-type APT layers and said fin material and between said p-type APT layer and said fin material, and wherein said etching further comprises removing said barrier layer in said uncovered portions.

7. The method as in claim 6, wherein said forming said barrier layer comprises epitaxial growth.

8. The method as in claim 6, wherein said barrier layer is a back-diffusion barrier layer formed of one of SiC and SiGe.

9. The method as in claim 1, wherein said n-type APT layer includes at least one of B, BF₂, and In, and said p-type APT layer includes at least one of P and As.

10. The method as in claim 1, further comprising forming a gate material over each of said discrete fins.

11. A method for forming a semiconductor fin device, said method comprising:

forming a first anti-punch through (APT) layer by epitaxial growth, said first APT layer being one of an n-type material and a p-type material;

forming a barrier layer over said first APT layer;

forming fin material over said barrier layer using epitaxial growth;

forming discrete fins from said fin material by patterning and etching;

forming shallow trench isolation (STI) structures in between said discrete fins;

removing some of said discrete fins and corresponding underlying portions of said first APT layer and said barrier layer, thereby exposing portions of said substrate;

forming a second APT layer by epitaxial growth on said portions of said substrate, said second APT layer being the other of said n-type and p-type material; and

forming a barrier layer over said second epitaxial APT layer and a fin material over said barrier layer in said regions,

thereby forming further discrete fins over said second APT layer.

12. The method as in claim 11, wherein said fin material comprises one of undoped Si and SiGe, said barrier layer comprises a back-diffusion barrier layer formed by epitaxial growth and said barrier layer is formed of at least one of SiC and SiGe.

13. The method as in claim 11, wherein said forming STI structures in between said discrete fins comprises depositing an oxide layer over said discrete fins and planarizing such that said STI structures and said discrete fins have co-planar upper surfaces and further comprising oxide etching after said forming said further discrete fins thereby receding said upper surfaces of said STI structures such that said discrete fins and said further discrete fins extend above said upper surfaces of said STI structures, and

further comprising forming a gate dielectric and a gate electrode over said discrete fins and over said further discrete fins.

14. The method as in claim 11, wherein said forming a first APT layer by epitaxial growth comprises epitaxial growth on a silicon substrate and said first APT layer includes Si and at least one of B, BF₂ and In.

15. The method as in claim 11, wherein said forming a first APT layer by epitaxial growth comprises epitaxial growth on a silicon substrate and said first APT layer includes Si and at least one of P and As and further comprising forming a gate dielectric and a gate electrode over said discrete fins and over said further discrete fins.

16. A method for forming a semiconductor fin device, said method comprising:

forming shallow trench isolation (STI) devices in a silicon substrate;

recessing portions of said silicon substrate between said STI devices to form receded Si surfaces such that said STI devices extend above said receded Si surfaces, each said receded Si surface forming a bottom of a trench bounded by opposed STI devices;

in some of said trenches, forming an n-type APT layer on said corresponding receded Si surface, forming a barrier layer over said n-type APT layer and forming a silicon fin material over said barrier layer thereby forming first Si fins; and

in other of said trenches, forming a p-type APT layer on said corresponding receded Si surface, forming a barrier layer over said p-type APT layer and forming a silicon fin material over said barrier layer thereby forming second Si fins.

17. The method as in claim 16, wherein said receded Si surfaces are above lowermost surfaces of said STI devices and wherein said forming an n-type APT layer and said forming a p-type APT layer each comprise said silicon fin material having an upper surface above an upper surface of said STI devices.

18. The method as in claim 16, wherein said forming an n-type APT layer is carried out using ion implantation and includes forming a masking material over said other of said trenches, and said forming a p-type APT layer is carried out using ion implantation and includes forming a masking material over said some of said trenches.

19. The method as in claim 16, further comprising forming a gate dielectric and a gate electrode over each of said first silicon fins and said second silicon fins.

20. The method as in claim 19, wherein each of said forming an n-type APT layer and said forming a p-type APT layer comprises epitaxial growth, said n-type APT layer includes Si and at least one of B, BF₂, and In, and said p-type APT layers includes Si and at least one of P and As, and further comprising forming FinFET devices using said first silicon fins and said second silicon fins.