Method of making a FinFET device

• US 8,497,177 B1
• Filed: 10/04/2012
• Issued: 07/30/2013
• Est. Priority Date: 10/04/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Xu, Jeff J., Lin, Hung-Ta, Nieh, Chun-Feng, Chang, Huicheng
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US13/645,305
• Time in Patent Office: 299 Days
• Field of Search: 438/283
• US Class Current: 438/283
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for fabricating a fin field-effect transistor (FinFET) device includes providing a substrate having a first fin at a first location, and epitaxially growing a second fin on the substrate at the first location. The epitaxial growth is performed at a first temperature. The method further includes performing a thermal annealing at a second temperature in oxygen ambient on the substrate with the second fin thereon to grow an interface wrapping over the second fin. The second temperature is higher than the first temperature.

Claims

1. A method for fabricating a fin field-effect transistor (FinFET) device, the method comprising:

providing a substrate having a first fin at a first location;

epitaxially growing a second fin on the substrate at the first location, the epitaxially growth being performed at a first temperature; and

performing a thermal annealing at a second temperature in an oxygen ambient on the substrate with the second fin thereon, to grow an interface wrapping over the second fin,

wherein the second temperature is higher than the first temperature.

2. The method of claim 1, wherein the interface has a substantially different composition than the epitaxially grown second fin.

3. The method of claim 1, wherein a thickness of the interface is controlled by the second temperature.

4. The method of claim 1, wherein the second fin includes a silicon germanium (SiGe) fin.

5. The method of claim 4, wherein the SiGe fin is formed by:

forming isolation regions on sides of the first fin;

recessing the first fin to form a recessing trench in the isolation regions;

epitaxially growing a SiGe layer with the first temperature on the recessed first fin to at least partially fill the recessing trench; and

recessing the isolation regions to laterally expose at least a portion of the epitaxially grown SiGe layer to form the SiGe fin.

6. The method of claim 1, wherein the second temperature is in a range from about 700°

C. to about 1500°

C.

7. The method of claim 5, wherein after the annealing process, the interface wrapping over the SiGe fin includes SiGe with a substantial different Ge concentration than the SiGe fin.

8. The method of claim 7, wherein the Ge concentration in the SiGe interface is substantially higher than that of the SiGe fin.

9. The method of claim 7, wherein the SiGe interface conformably wraps the SiGe fin.

10. The method of claim 1, wherein a SiO₂ interface is formed on the SiGe interface during the thermal annealing process.

11. The method of claim 10, further comprising:

removing the SiO₂ interface by an etching process.

12. A method for fabricating a fin field-effect transistor (FinFET) device, the method comprising:

providing a substrate;

recessing the substrate to form a plurality of first fins;

forming isolation regions between the first fins on the substrate;

recessing the first fins to form at least one recessing trench in the isolation regions;

epitaxially growing silicon germanium (SiGe) layer with a first temperature in the recessing trench;

recessing the isolation regions to expose an upper portion of the SiGe layer to form a SiGe fin; and

performing a thermal anneal at a second temperature in an oxygen ambient to the SiGe fin to form a SiGe interface with a substantial different Ge concentration than the SiGe fin.

13. The method of claim 12, wherein the second temperature is higher than the first temperature.

14. The method of claim 13, wherein the second temperature is in a range from about 700°

C. to about 1500°

C.

15. The method of claim 12, wherein a Ge concentration in the SiGe interface is substantially higher than the one in the SiGe fin.

16. The method of claim 12, wherein a thickness of the SiGe interface is adjustable by adjusting the annealing condition including the second temperature and a duration of the anneal.

17. The method of claim 12, wherein the SiGe interface is formed to conformably wrap over the SiGe fin.

18. The method of claim 12, wherein a SiO₂ interface is formed on the SiGe interface during the annealing.

19. The method of claim 18, further comprising:

removing the SiO₂ interface; and

then depositing a Si capping layer on the SiGe interface.

20. A method for fabricating a fin field-effect transistor (FinFET) device, the method comprising:

providing a silicon (Si) substrate;

etching back a portion of the Si substrate to form a plurality of Si fins;

forming isolation regions between the Si fins;

recessing the Si fins to form recessing trenches on the Si substrate;

epitaixially growing a silicon germanium (SiGe) layer with a first temperature in the recessing trenches;

recessing the isolation regions to expose an upper portion of the SiGe layer, wherein the upper portion of the SiGe layer forms a plurality of SiGe fins;

performing a thermal annealing in an oxygen ambient on the SiGe fins by using a second temperature which is higher than the first temperature, wherein a conformal SiGe interface is formed that wraps over the SiGe fins, wherein the SiGe interface has a substantial higher Ge concentration than the SiGe fins, and wherein a SiO₂ interface is formed over the SiGe interface;

removing the SiO₂ interface by an etching process; and

after removing the SiO₂ interface, forming a Si capping layer on the SiGe interface.