Protecting semiconducting oxides

• US 8,497,506 B2
• Filed: 09/04/2012
• Issued: 07/30/2013
• Est. Priority Date: 10/26/2007
• Status: Active Grant

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Chabinyc, Michael L., Ng, Tse N.
• Primary Examiner(s): MENZ, DOUGLAS M
• Application Number:
  US13/603,383
• Publication Number:
  US 20120326149A1
• Time in Patent Office: 329 Days
• Field of Search: 257/57, 257/59
• US Class Current: 257/57
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

In transistor structures such as thin film transistors (TFTs) in an array of cells, a layer of semiconducting oxide material that includes a channel is protected by a protective layer that includes low-temperature encapsulant material. The semiconducting oxide material can be a transition metal oxide material such as zinc oxide, and can be in an active layered substructure that also includes channel end electrodes. The low-temperature encapsulant can, for example, be an organic polymer such as poly(methyl methacrylate) or parylene, deposited on an exposed region of the oxide layer such as by spinning, spincasting, evaporation, or vacuum deposition or an inorganic polymer deposited such as by spinning or liquid deposition. The protective layer can include a lower sublayer of low-temperature encapsulant on the exposed region and an upper sublayer of inorganic material on the lower sublayer. For roll-to-roll processing, a mechanically flexible, low-temperature substrate can be used.

Claims

1. A transistor structure comprising:

a gate electrode;

a gate dielectric layer over the gate electrode;

a layered structure over the gate dielectric layer, the layered structure including;

a source electrode;

a drain electrode; and

a semiconducting transition metal oxide layer in which a channel is defined, the channel being electrically connected between the source and drain electrodes;

the oxide layer having an exposed region;

a first protective layer on the oxide layer'"'"'s exposed region, the first protective layer including an organic polymer and being structured to protect the oxide layer; and

a second, inorganic protective layer over the first protective layer.

2. The transistor structure of claim 1 in which the source and drain electrodes are on the layered structure adjacent the oxide layer'"'"'s exposed region, the first protective layer is also on the source and drain electrodes, and the second, inorganic protective layer is on the first protective layer;

the first protective layer and the second, inorganic protective layer having a via defined through them to allow electrical connection to one of the source and drain electrodes.

3. A transistor structure comprising:

a mechanically flexible, low-temperature substrate;

a gate electrode over the substrate;

a gate dielectric layer over the gate electrode;

a layered structure over the gate dielectric layer, the layered structure including a semiconducting oxide layer in which a channel is defined;

the oxide layer having an exposed region; and

a low-temperature protective layer on the oxide layer'"'"'s exposed region, the low-temperature protective layer being structured to protect the oxide layer, wherein the low-temperature protective layer includes;

a lower sublayer that includes a low-temperature encapsulant and is on the oxide layer'"'"'s exposed region; and

an upper sublayer on the lower sublayer, the upper sublayer including inorganic material.

4. The transistor structure of claim 3 in which the low-temperature protective layer is mechanically flexible.

5. An article comprising:

a substrate; and

a layered structure on the substrate;

the layered structure including;

a gate layer that includes gate electrodes;

a gate dielectric layer over a set of the gate electrodes;

an active layered substructure over the gate dielectric layer, the active layered substructure including a layer of semiconducting oxide material;

in operation, the active layered substructure including;

a set of one or more channels defined in the layer of semiconducting oxide material, each channel being over at least one of the gate electrodes; and

a protective layer over the active layered substructure, the protective layer including low-temperature encapsulant and being structured to protect the semiconducting oxide material, wherein the protective layer includes;

a lower sublayer that includes the low-temperature encapsulant and is on the active layered substructure; and

an upper sub layer on the lower sublayer, the upper sub layer including inorganic material.

6. The article of claim 5 in which the layered structure includes an array of cells, each of a set of the cells including a respective subset of the set of channels.

7. The article of claim 6 in which each of the cells further includes:

a respective cell electrode;

one or more respective channel end electrodes, each of the cell'"'"'s channel end electrodes being electrically connected to an end of a channel in the cell'"'"'s respective subset of channels; and

conductive via material extending through the protective layer and electrically connecting the respective cell electrode and one of the cell'"'"'s respective channel end electrodes.

8. The article of claim 7 in which the conductive via material extends through both the lower and upper sublayers;

the cell electrode being over the upper sub layer.

9. The article of claim 5 in which the substrate is a mechanically flexible, low-temperature substrate, the protective layer also being mechanically flexible.