Array substrate for liquid crystal display device and method of fabricating the same

• US 8,497,507 B2
• Filed: 12/26/2007
• Issued: 07/30/2013
• Est. Priority Date: 12/26/2006
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Yang, Joon-Young
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): CHOUDHRY, MOHAMMAD M
• Application Number:
  US12/003,488
• Publication Number:
  US 20080210942A1
• Time in Patent Office: 2,043 Days
• Field of Search: 257/59
• US Class Current: 257/59
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

An array substrate for a liquid crystal display device includes a gate line on a substrate; a gate insulating layer on the gate line; a data line crossing the gate line; a gate electrode connected to the gate line; an active layer on the gate insulating layer and overlapping the gate electrode; first and second ohmic contact layers on the active layer, the first and second ohmic contact layers spaced apart from each other by a first distance; first and second barrier patterns spaced apart from each other by the first distance and on the first and second ohmic contact layers, respectively. The active layer is exposed through the first and second barrier patterns; source and drain electrodes spaced apart from each other by a second distance greater than the first distance and on the first and second barrier patterns, respectively.

Claims

1. An array substrate for a liquid crystal display device, comprising:

a gate line on a substrate;

a gate insulating layer on the gate line;

a data line crossing the gate line;

a gate electrode connected to the gate line;

an active layer on the gate insulating layer and overlapping the gate electrode;

first and second ohmic contact layers on the active layer, the first and second ohmic contact layers spaced apart from each other by a first distance;

first and second barrier patterns spaced apart from each other by the first distance and on the first and second ohmic contact layers, respectively, wherein the active layer is exposed through the first distance between the first and second barrier patterns;

source and drain electrodes spaced apart from each other by a second distance greater than the first distance and on the first and second barrier patterns, respectively, the source electrode being connected to the data line;

a passivation layer on the substrate and directly contacting a top surface of the first and second barrier patterns, wherein the passivation layer includes a drain contact hole; and

a pixel electrode on the passivation layer and connected to the drain electrode via the drain contact hole,

wherein the first and second barrier patterns include at least one of molybdenum (Mo) and molybdenum-titanium alloy (MoTi).

2. The substrate according to claim 1, wherein the source and drain electrodes include at least one of copper (Cu), copper-titanium alloy (Cu—

Ti), aluminum (Al) and Al alloy (AlNd).

3. The substrate according to claim 1, wherein each of the first ohmic contact layers, the first barrier pattern, and the source electrode is symmetric about a center line of the gate electrode to the second ohmic contact layer, the second barrier pattern, and the drain electrode, respectively.

4. The substrate according to claim 1, wherein the first and second barrier patterns define a space therebetween that corresponds with a space defined between the first and second ohmic contact layers.

5. A method of fabricating an array substrate for a liquid crystal display device, comprising:

forming a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line;

forming a gate insulating layer on the gate electrode and the gate line;

forming an active layer on the gate insulating layer, an impurity-doped amorphous silicon pattern on the active layer and a metal pattern on the impurity-doped amorphous silicon pattern on the active layer, each of the active layer, the impurity-doped amorphous silicon pattern and the metal pattern overlapping the gate electrode;

forming a first metal layer on the metal pattern;

forming first and second photosensitive material patterns on the first metal layer and corresponding to the metal pattern, the first and second photosensitive material patterns spaced apart from each other by a first distance;

patterning the first metal layer using the first and second photosensitive material patterns as an etching mask to form a source electrode, a drain electrode and a data line, the source and drain electrodes on the metal pattern and spaced apart from each other by a second distance being greater than the first distance, the data line crossing the gate line and connected to the source electrode;

etching the metal pattern and the impurity-doped amorphous silicon pattern to form first and second barrier patterns from the metal pattern under the source and drain electrodes and first and second ohmic contact layers under the first and second barrier patterns, wherein the first barrier pattern and the first ohmic contact pattern are spaced apart from the second barrier pattern and the second ohmic contact pattern by the first distance;

forming a passivation layer on the substrate and directly contacting a top surface of the first and second barrier patterns, wherein the passivation layer includes a drain contain hole; and

forming a pixel electrode on the passivation layer and connected to the drain electrode via the drain contact hole,

wherein the metal pattern includes at least one of molybdenum (Mo) and molybdenum-titanium alloy (MoTi).

6. The method according to claim 5, wherein etching the metal pattern and the impurity-doped amorphous silicon pattern includes:

anisotropically dry-etching the metal pattern and the impurity-doped amorphous silicon pattern using the first and second photosensitive material patterns as an etching mask to expose the active layer; and

removing the first and second photosensitive material patterns.

7. The method according to claim 5, wherein the source and drain electrodes include at least one of copper (Cu), copper-titanium alloy (Cu—

Ti), aluminum (Al) and Al alloy (AlNd).

8. The method according to claim 5, wherein the first and second barrier patterns define a space therebetween that corresponds with a space defined between the first and second ohmic contact layers.

9. The method according to claim 5, wherein the first metal layer is patterned by a wet-etching using an etchant, and wherein the metal pattern is not etched by the etchant.