Self-aligned contact for trench MOSFET

• US 8,497,551 B2
• Filed: 06/02/2010
• Issued: 07/30/2013
• Est. Priority Date: 06/02/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kalnitsky, Alex, Tuan, Hsiao-Chin, Wu, Kuo-Ming, Huang, Wei Tsung
• Primary Examiner(s): Tran, Thanh Y
• Application Number:
  US12/792,025
• Publication Number:
  US 20110298045A1
• Time in Patent Office: 1,154 Days
• Field of Search: 257/331, 257/334, 257/302, 257/330, 257/332, 257/341, 257/336, 257/E29.2, 257/E29.201, 257/E21.549, 257/E21.655, 438/270, 438/272, 438/424, 438/427
• US Class Current: 257/331
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

The process methods and structures mentioned above for creating a trench MOSFET enables self-aligned contacts to be formed to allow decreasing pitch size for trench MOSFET. The self-aligned contacts are formed by etching exposed silicon areas without using lithographical mask and alignment. As a result, the allowance for alignment can be saved and the pitch size can be decreased.

Claims

1. A trench metal oxide semiconductor field effect transistor (MOSFET) structure on a substrate, comprising:

a first trench and a second trench on the substrate, wherein both the first trench and the second trench are lined with a gate dielectric layer and filled with gate polysilicon;

a self-aligned source contact between the first trench and the second trench, wherein the self-aligned source contact is connected to a source metal;

a gate contact above the first trench, wherein the gate contact is connected to a gate metal and to the gate polysilicon in the first trench; and

a source region surrounding the self-aligned source contact,

wherein the source region comprises a convex surface and a curved surface directly above the convex surface.

2. The trench MOSFET structure of claim 1, wherein the trench MOSFET is an N-MOSFET or a P-MOSFET.

3. The trench MOSFET structure of claim 1, wherein the trench MOSFET is part of a power device, which operates between about 1.8V to about 600V.

4. The trench MOSFET structure of claim 1, wherein a pitch of the trench MOSFET is between about 0.5 μ

m to about 5 μ

m.

5. The trench MOSFET structure of claim 1, wherein a doped substrate region below the first and the second trenches is a drain region of the trench MOSFET.

6. The trench MOSFET structure of claim 5, wherein the trench MOSFET is N-type and the source region and the drain region are doped with N-type dopants.

7. The trench MOSFET structure of claim 1, wherein there is a third trench next to the second trench, and wherein the second trench is between the first and the third trenches, and wherein a distance between the first and the second trenches is between about 0.5 μ

m to about 5 μ

m.

8. The trench MOSFET structure of claim 1, wherein a silicon region directly below the self-aligned source contact has a higher dopant concentration than a surrounding region.

9. The trench MOSFET structure of claim 1, wherein the gate dielectric layer has a thickness between about 40 Å

to about 2000 Å

.

10. The trench MOSFET structure of claim 1, wherein the source region is above a surface of gate polysilicon in the second trench.

11. A trench metal oxide semiconductor field effect transistor (MOSFET) structure on a substrate, comprising:

a first trench, a second trench, and a third trench on the substrate, wherein the first trench, the second trench, and the third trench are lined with a gate dielectric layer and filled with gate polysilicon;

a first self-aligned source contact between the first trench and the second trench and a second self-aligned source contact between the second trench and the third trench, wherein both the first and the second self-aligned source contacts are connected to a source metal;

a gate contact above the first trench, wherein the gate contact is connected to a gate metal and to the gate polysilicon in the first trench; and

a first source region surrounding the first self-aligned source contact and a second source region surrounding the second self-aligned source contact, wherein both the first and the second source regions are convex-shaped, and wherein the first source region and the second source region are above an upper surface of the gate polysilicon in the second trench.

12. The trench MOSFET structure of claim 11, wherein a doped substrate region below the first, the second, and the third trenches is a drain region of the trench MOSFET.

13. The trench MOSFET structure of claim 11, wherein silicon regions directly below the first and the second self-aligned source contacts have higher dopant concentrations than surrounding regions.

14. A transistor comprising:

a substrate doped with a first type dopant;

an epitaxial layer over the substrate, the epitaxial layer having a doped portion doped with a second type dopant and a source region doped with the first type dopant;

a first gate structure in the epitaxial layer, at least a portion of the first gate structure being adjacent to the doped portion, the first gate structure comprising;

a gate electrode; and

a gate dielectric layer sandwiched between the gate electrode and the epitaxial layer;

a second gate structure in the epitaxial layer, at least a portion of the second gate structure being adjacent to the doped portion, the second gate structure comprising;

a gate electrode; and

a gate dielectric layer sandwiched between the gate electrode and the epitaxial layer;

a source contact between the first gate structure and the second gate structure, the source region being adjacent to the source contact and convex-shaped with a convex surface facing the substrate; and

a gate contact electrically coupled to the gate electrode of the first gate structure and the gate electrode of the second gate structure,

wherein the source region is above an upper surface of the second gate structure.

15. The transistor of claim 14, wherein a pitch between the first gate structure and the second gate structure ranges from about 0.5 μ

m to about 5 μ

m.

16. The transistor of claim 14, wherein the substrate is usable as a drain terminal of the transistor.

17. The transistor of claim 14, further comprising:

a third gate structure in the epitaxial layer, at least a portion of the third gate structure being adjacent to the doped portion, the third gate structure comprising;

a gate electrode; and

a gate dielectric layer sandwiched between the gate electrode and the epitaxial layer; and

another source contact between the second gate structure and the third gate structure.

18. The transistor of claim 17, wherein a pitch between the second gate structure and the third gate structure ranges from about 0.5 μ

m to about 5 μ

m.

19. The transistor of claim 14, wherein the gate dielectric layer of the second gate structure has a thickness ranging from about 40 Å

to about 2000 Å

.

20. The transistor of claim 14, wherein the source region further comprises a curved surface directly above the convex surface.