Fractional-rate phase frequency detector
First Claim
Patent Images
1. A circuit, comprising:
- phase detector circuitry coupled to receive (a) a serial data bit stream clocked by a full rate clock signal with a full rate frequency, and (b) at least two fractional clock signals with a fractional rate frequency that is a binary integer fraction of the full rate frequency;
Clk-I and Clk-Q which lags in phase Clk-I by substantially 90°
;
the phase detector circuitry including;
sampling circuitry configured to sample the at least Clk-I and Clk-Q fractional clock signals with the serial data bit stream to generate at least first and second phase differences between a sampling bit edge of the serial data bit stream and respective clock edges of the at least Clk-I and Clk-Q fractional clock signals closest in time to the sampling bit edge; and
phase difference circuitry responsive to the at least first and second phase differences to provide a phase difference signal corresponding to the difference in phase between the edges of the serial data bit stream and at least the Clk-I fractional clock signal, and thereby corresponding to the difference in phase between the full rate clock signal and at least the Clk-I fractional clock signal.
1 Assignment
0 Petitions
Accused Products
Abstract
A phase frequency detector detects the difference between the edges of a fractional-rate recovered clock signal and the edges within a serial data bit stream, where the edges within the serial data bit stream correspond with the edges of a full-rate clock signal that was used to clock the serial data bit stream.
-
Citations
17 Claims
-
1. A circuit, comprising:
-
phase detector circuitry coupled to receive (a) a serial data bit stream clocked by a full rate clock signal with a full rate frequency, and (b) at least two fractional clock signals with a fractional rate frequency that is a binary integer fraction of the full rate frequency;
Clk-I and Clk-Q which lags in phase Clk-I by substantially 90°
;the phase detector circuitry including; sampling circuitry configured to sample the at least Clk-I and Clk-Q fractional clock signals with the serial data bit stream to generate at least first and second phase differences between a sampling bit edge of the serial data bit stream and respective clock edges of the at least Clk-I and Clk-Q fractional clock signals closest in time to the sampling bit edge; and phase difference circuitry responsive to the at least first and second phase differences to provide a phase difference signal corresponding to the difference in phase between the edges of the serial data bit stream and at least the Clk-I fractional clock signal, and thereby corresponding to the difference in phase between the full rate clock signal and at least the Clk-I fractional clock signal. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A circuit, comprising:
-
first phase detector circuitry coupled to receive (a) a serial data bit stream clocked by a full rate clock signal with a full rate frequency, and (b) two fractional clock signals with a half rate frequency that is one half the full rate frequency;
Clk-I and Clk-Q which lags in phase Clk-I by substantially 90°
;the first phase detector circuitry including; first sampling circuitry configured to sample the Clk-I and Clk-Q fractional clock signals with the serial data bit stream to generate first and second phase differences between a sampling bit edge of the serial data bit stream and respective clock edges of the Clk-I and Clk-Q fractional clock signals closest in time to the sampling bit edge; and first phase difference circuitry responsive to the first and second phase differences to provide a first phase difference signal corresponding to the difference in phase between the edges of the serial data bit stream and at least the Clk-I fractional clock signal, and thereby corresponding to the difference in phase between the full rate clock signal and at least the Clk-I fractional clock signal; second phase detector circuitry coupled to receive (a) the serial data bit stream clocked by a full rate clock signal with a full rate frequency, and (b) two fractional clock signals both with a frequency corresponding to the fractional rate frequency of the Clk-I fractional clock signal;
Clk-45 which lags in phase the Clk-I fractional clock signal by substantially 45°
, and Clk-135 which lags the Clk-I fractional clock signal by substantially 135°
;the second phase detector circuitry detector circuitry including; second sampling circuitry configured to sample the Clk-45 and Clk-135 fractional clock signals with the serial data bit stream to generate third and fourth phase differences between the sampling bit edge of the serial data bit stream and respective clock edges of the Clk-45 and Clk135 fractional clock signals closest in time to the sampling bit edge; and second phase difference circuitry responsive to the third and fourth phase differences to provide a second phase difference signal corresponding to the difference in phase between the edges of the serial data bit stream and at least the Clk-I fractional clock signal; and frequency detector circuitry responsive to the first and second phase difference signals to provide a frequency difference signal corresponding to the difference in frequency between the full rate clock signal used to clock the serial data bit stream and at least the Clk-I fractional clock signal. - View Dependent Claims (8, 9, 10, 11, 12)
-
-
13. A method, comprising:
-
receiving (a) a serial data bit stream clocked by a full rate clock signal with a full rate frequency, and (b) at least two fractional clock signals with a fractional rate frequency that is a binary integer fraction of the full rate frequency;
Clk-I and Clk-Q which lags in phase Clk-I by substantially 90°
;sampling the at least Clk-I and Clk-Q fractional clock signals with the serial data bit stream to determine at least first and second phase differences between a sampling bit edge of the serial data bit stream and respective clock edges of the at least Clk-I and Clk-Q fractional clock signals closest in time to the sampling bit edge; and providing, in response to the at least first and second phase differences, a phase difference signal corresponding to the difference in phase between the edges of the serial data bit stream and at least the Clk-I fractional clock signal, and thereby corresponding to the difference in phase between the full rate clock signal and at least the Clk-I fractional clock signal. - View Dependent Claims (14, 15, 16, 17)
-
Specification