Voltage programmed pixel circuit, display system and driving method thereof

• US 8,497,825 B2
• Filed: 08/17/2011
• Issued: 07/30/2013
• Est. Priority Date: 01/28/2005
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Nathan, Arokia, Chaji, Gholamreza, Servati, Peyman
• Primary Examiner(s): Lao, Lun-Yi
• Assistant Examiner(s): ABDIN, SHAHEDA A
• Application Number:
  US13/211,732
• Publication Number:
  US 20120001888A1
• Time in Patent Office: 713 Days
• Field of Search: 345/76, 345/90, 345/92, 345/93, 345/95, 345/100, 345/204, 345/206, 345/214, 345/82, 349 41- 43, 349/151, 313/463, 315/169.3
• US Class Current: 345/76
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2300/0866 by means of changes in the pixel supply voltage
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 5/00 Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators image data processing or generation, in general G06T
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

A voltage programmed pixel circuit, display system having the pixel circuit and driving method thereof is provided. The pixel circuit includes a light emitting device, a driving transistor connected to the light emitting device and a programming circuit. The programming circuit adjusts a pixel current during a programming cycle of the pixel circuit.

Claims

1. A pixel circuit comprising:

a light emitting device having a first electrode and a second electrode;

a driving transistor having a gate terminal, a first terminal and a second terminal, the first terminal of the driving transistor being connected to the first electrode of the light emitting device;

a first capacitor having first and second terminals, the first terminal of the first capacitor being connected to the gate terminal of the driving transistor, the second terminal of the first capacitor being connected to the first terminal of the driving transistor and the first electrode of the light emitting device;

a first switch transistor having a gate terminal, a first terminal and a second terminal, the first terminal of the first switch transistor being coupled to the gate terminal of the driving transistor and the first terminal of the first capacitor; and

a programming circuit having a programming transistor,

the programming transistor having a gate terminal, a first terminal and a second terminal,

the first terminal being connected to the first electrode of the light emitting device,

the gate of said programming transistor directly being connected to a first data line,

wherein,

during a programming cycle of the pixel circuit, the programming transistor converts a voltage from the first data line to a current to adjust the voltage at said first terminal of said driving transistor to program a pixel current of said driving transistor, and

during a driving cycle of the pixel circuit, the programming transistor is turned off and the light emitting device is driven with the pixel current from said driving transistor.

2. A pixel circuit according to claim 1, wherein the programming circuit includes a second switch transistor and a second capacitor, the second switch transistor having a gate terminal, a first terminal and a second terminal, the second capacitor having a first terminal and a second terminal, the gate terminal of the programming transistor being connected to the first terminal of the second switch transistor and the first terminal of the second capacitor.

3. A pixel circuit according to claim 2, wherein voltage provided to the pixel circuit is determined so that during the programming cycle, a programming voltage is written into the second capacitor through the second switch transistor while during the driving cycle of the pixel circuit, a reset voltage is written into the second capacitor to turn off the programming transistor.

4. A pixel circuit according to claim 1, wherein the light emitting device includes an organic light emitting diode (OLED), and at least one of the transistors is a n-type or p-type thin-film transistor (TFT).

5. A pixel circuit according to claim 1, wherein at least one of the switch, programming and driving transistors is a n-type or p-type thin film transistors (TFTs).

6. A pixel circuit according to claim 1, wherein the light emitting device is an inverted (NIP) or non-inverted (PIN) organic light emitting device (OLED).

7. A pixel circuit according to claim 1, wherein the programming transistor is a thin film transistor (TFT), and the pixel circuit incorporates a short term biasing condition in which a programming TFT is stable.

8. A pixel circuit according to claim 1, wherein the light emitting device is an (OLED), and wherein the programming transistor is under stress for a small fraction of frame time and adjusting the pixel current, while the driving transistor drives the OLED.

9. A display system, comprising:

a display array including a plurality of pixel circuits according to claim 1;

a driver system for driving the display array to establish a programming cycle and a driving cycle; and

a controller for controlling the driver system.

10. A display system according to claim 9, wherein the driver system drives a first select line connected to the gate terminal of the first switch transistor, a second select line connected to the second terminal of the programming transistor, a first signal line connected to the gate terminal of the programming transistor;

and a second signal line connected to the second terminal of the switch transistor.

11. A display system according to claim 10, wherein the plurality of pixel circuits are arranged in rows and columns, each of the first and second select lines being shared between common row pixel circuits in the display array, and each of the first and second signal lines being shared between common column pixel circuits in the display array.

12. A display system according to claim 9, wherein the driver system drives a first select line connected to the gate terminal of the first switch transistor, a second select line connected to the second terminal of the programming transistor, a signal line connected to the gate terminal of the programming transistor;

and a voltage line connected to the second terminal of the first switch transistor and the second terminal of the driving transistor.

13. A display system according to claim 12, wherein the plurality of pixel circuits are arranged in rows and columns, each of the first select line, the second select line, and the voltage line being shared between common row pixel circuits in the display array, and the signal line being shared between common column pixel circuits in the display array.

14. A display system according to claim 12, wherein during the programming cycle of nth row, the second select line is used to provide a predetermined voltage, and during the programming cycle of the (n+1)th row, the second select line is used to provide the address signal of (n+1)th row.

15. A display system according to claim 14, wherein during the programming cycle of nth row, the second select line is used to provide a predetermined voltage, and during the programming cycle of the (n+1)th row, the second select line is used to provide the address signal of (n+1)th row.

16. A display system according to claim 9, wherein the programming circuit includes a second switch transistor and a second capacitor, the second switch transistor having a gate terminal, a first terminal and a second terminal, the second capacitor having a first terminal and a second terminal, the gate terminal of the programming transistor being connected to the first terminal of the second switch transistor and the first terminal of the second capacitor.

17. A display system according to claim 16, wherein the driver system drives a first select line connected to the gate terminal of the first switch transistor, a second select line connected to the second terminal of the programming transistor, a first signal line connected to the second terminal of the second switch transistor;

and a second signal line connected to the second terminal of the first switch transistor.

18. A display system according to claim 17, wherein the plurality of pixel circuits are arranged in rows and columns, each of the first and second select lines being shared between common row pixel circuits in the display array, and each of the first and second signal lines being shared between common column pixel circuits in the display array.

19. A display system according to claim 16, wherein the driver system drives a first select line connected to the gate terminal of the first switch transistor, a second select line connected to the second terminal of the programming transistor, a signal line connected to the second terminal of the second switch transistor;

and a voltage line connected to the second terminal of the first switch transistor and the second terminal of the driving transistor.

20. A display system according to claim 19, wherein the plurality of pixel circuits are arranged in rows and columns, each of the first select line, the second select line, and the voltage line being shared between common row pixel circuits in the display array, and the signal line being shared between common column pixel circuits in the display array.

21. A display system according to claim 19, wherein during the programming cycle of nth row, the second select line is used to provide a predetermined voltage, and during the programming cycle of the (n+1)th row, the second select line is used to provide the address signal of (n+1)th row.

22. A display system according to claim 16, wherein during the programming cycle of nth row, the second select line is used to provide a predetermined voltage, and during the programming cycle of the (n+1)th row, the second select line is used to provide the address signal of (n+1)th row.

23. A method of driving a pixel circuit, the pixel circuit comprising a light emitting device having a first electrode and a second electrode;

a driving transistor having a gate terminal, a first terminal and a second terminal, the first terminal of the driving transistor being connected to the first electrode of the light emitting device;

a first capacitor having first and second terminals, the first terminal of the first capacitor being connected to the gate terminal of the driving transistor, the second terminal of the first capacitor being connected to the first terminal of the driving transistor and the first electrode of the light emitting device;

a first switch transistor having a gate terminal, a first terminal and a second terminal, the first terminal of the first switch transistor being connected the gate terminal of the driving transistor and the first terminal of the first capacitor; and

a programming circuit having a programming transistor, the programming transistor having a gate terminal, a first terminal and a second terminal, the first terminal being connected to the first electrode of the light emitting device; and

the gate of said programming transistor directly being coupled to a first data line,

the method comprising;

at a programming cycle of the pixel circuit, converting a voltage supplied to the gate of the programming transistor from the first data line to a current to adjust the voltage at said first terminal of said driving transistor to program a pixel current of said driving transistor;

at a driving cycle of the pixel circuit, turning off the programming transistor and driving the light emitting device with the pixel current from the driving transistor.

24. A method of driving a pixel circuit according to claim 23, wherein at least one of the switch, programming and driving transistors is a n-type or p-type thin film transistors (TFTs).

25. A method of driving a pixel circuit according to claim 23, wherein the light emitting device in the pixel circuit is an inverted (NIP) or non-inverted (PIN) organic light emitting device (OLED).

26. A method of driving a pixel circuit according to claim 23, wherein the pixel circuit further comprises a first select line connected to the gate terminal of the first switch transistor, a second select line connected to the second terminal of the programming transistor, a first signal line connected to the gate terminal of the programming transistor;

and a second signal line connected to the second terminal of the switch transistor.

27. A method of driving a pixel circuit according to claim 23, wherein the pixel circuit further comprises a first select line connected to the gate terminal of the first switch transistor, a second select line connected to the second terminal of the programming transistor, a signal line connected to the gate terminal of the programming transistor;

and a voltage line connected to the second terminal of the first switch transistor and the second terminal of the driving transistor.

28. A method of driving a pixel circuit according to claim 23, wherein the programming circuit further comprises a second switch transistor and a second capacitor, the second switch transistor having a gate terminal, a first terminal and a second terminal, the second capacitor having a first terminal and a second terminal, the gate terminal of the programming transistor being connected to the first terminal of the second switch transistor and the first terminal of the second capacitor.

29. A method of driving a pixel circuit according to claim 28, wherein the pixel circuit further comprises a first select line connected to the gate terminal of the first switch transistor, a second select line connected to the second terminal of the programming transistor, a first signal line connected to the gate terminal of the programming transistor;

and a second signal line connected to the second terminal of the switch transistor.

30. A method of driving a pixel circuit according to claim 28, wherein the pixel circuit further comprises a first select line connected to the gate terminal of the first switch transistor, a second select line connected to the second terminal of the programming transistor, a signal line connected to the gate terminal of the programming transistor;

and a voltage line connected to the second terminal of the first switch transistor and the second terminal of the driving transistor.